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OPC-1 gets subroutines!

A project log for OPC-1 CPU for CPLD

A one-page CPU: spec, HDL, emulator and macro assembler each in one page. Fits in XC9572 CPLD.

ed-sEd S 06/13/2017 at 13:490 Comments

We made an update, adding a link register and three instructions, which give us subroutine capability. There's still no stack!

The cost of this update, in fitting in the CPLD, was one address bit, so we move down from a 12 bit address space to 11 bits.

JSR stores the current PC in the link register and the accumulator - the PC is 11 bits, the accumulator only 8, so we needed a 3 bit link register. RTS copies the link and accumulator into the PC. That's almost enough, but to save a return address we need access to the link register, so LXA exchanges the link register and the accumulator.

In fact here's the spec on the subject:

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