The discovery of the 74HC259 has been an eye-opener. See 35. Enabling discovery
The heart of the YGREC is its "register set". Actually it's more than a standard register set, it's a sort of hub where data are shuffled and moved around...
The storage part is built with 74HC259. They are driven with the result bus, as well as the address of the result. One address bit must be a complementary pair to select the right '259. The last input signal is the latch enable, which is sent by the control logic, from the condition result.
The outputs go to the multiplexers. Well, most outputs, because the registers corresponding to PC, D1 and D2 are ignored, and the outputs for I/O go directly to the output bus.
Similarly, the MUX will input data from the PC, D1 and D2 latches, as well as the IO inputs. That leaves only 9 bits that are effectively used in the 259s, so maybe if we remove one more register, we can save one 259 per bitslice ?
Output ports get relegated to 74HC573/4 on a I/O board, for example, hooked to the result bus. The PC, D1 and D2 are also HC573/4s. The last external latch could be a third memory port, D3.
The new register map is as follows:
|D1||*||overwritten by RES and DRAM|
|D2||*||overwritten by RES and DRAM|
|D3||overwritten by RES and DRAM|
|PC||PC+1 (some pipelining somewhere?)|
A3/D3 has eaten into the T1/T2/T3 pool so the remaining T is renamed as R5.
Suddenly, the register map looks more like the YASEP's...
Not only is the register map heterogeneous, but also the subset addressed by the field SRC is probably not ordered like the field SRCX. This is because the '259 writes to a different set of registers:
- SRC: A1, D1, A2, D2, R1, R2, R3, R4
- 259: A1, A2, A3, R1, R2, R3, R4, R5
|259||R1, R2, R3, R4,|
|ext. 573||D1, D2||PC|
IO1, IO2, IO3, IO4
Yes it's totally messed up!
It would be so much simpler if the SRC subset was the whole SRCX set but it's ruled out by the instruction format and the large MUX that is required to make it work... I want the damned thing to be binary compatible with the other generations (relay, germanium, silicon...)
Anyway, reducing the circuit count is a significant enough saving to justify changing the register map.
So now that's one '259 per bitslice for the latches, and there are 8 external registers (16×573/4) for the other things.
- 4×573/4 for the output ports, tied to the result bus. They can be located on a different board for easier manipulations and modularity.
- 3×573 for the D1,D2,D3 : there will be some steering/buffering of the data bus because the result bus and the R/W bus will talk to each other. This, in itself, will be an interesting log to write...
- PC comes from 4× '193 but there is some timing issues to consider... another log to write !
that's 14 '573/4 (I'll decide depending on the timing constraints).
The inputs : we have a MUX16 and a MUX8, all made from 74HC251. I tried to find a MUX16 but there is no 74HC150 or 74HC250 available in the market (maybe a few LS ones but they require more power and a HCT part later).