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OPC-5 developments

A project log for OPC-5 - a CPU for FPGA, in one page

A 16-bit CPU, with 16 registers, described in 66 lines of code - with HDL, emulators and a macro assembler.

Ed SEd S 07/13/2017 at 20:200 Comments

Our first cut of OPC-5, the one-page CPU for FPGA, had a fixed two-word instruction format. But often the operand word will be zero, so we've used one additional bit of the instruction word to cover that case, and now we have a variable-length instruction machine.

We've also doubled the instruction count: instead of four basic instructions, with a choice of absolute or indirect addressing (load, store, add, nand) we've moved up to eight: load, store, add, sub, and, or xor and ror, still with the addressing choice. That should be more comfortable, even though the earlier set was enough for any program. We can improve code density and performance by offering more power in the instruction set.

In fact, after a little consideration, we've removed SUB, and instead split out an ADD and an ADC. We also changed the ROR to be a 17-bit rotate including the carry - this should help with multi-word arithmetic.

And finally (for now) we expanded our predicate idea - we still have one bit to spare - instead of just two bits for predication on zero and carry, we added an invert bit so we could make each instruction conditional on the flags being clear or set. In the case of instructions which modify r15, the program counter, that gives us a family of conditional branches (absolute or relative.)

Here's the result: https://github.com/revaldinho/opc/blob/a2bf708b30d634a22ee7396650b926b2f0becb75/docs/opc5spec.md

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