My try on the one page cpu challange, the cpu itself without the alu is just 48 lines of python code and is convertable to vhdl or verilog with the myhdl software/hardware ( description language. The op-code is 8 bit wide and the Databitwidth of the CPU is configurable.

Not jet finished, i think the assembler would need to insert some nop at specific places to work or something like this, this was added to optimize code size (lines of code) of the cpu itself.

Motivated to publish because of this: