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MARK-II

Simple SoC written in VHDL.

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Welcome on the page about MARK-II project! MARK-II is hobby project. It is simple System on Chip (SoC) with custom CPU and peripherals written in VHDL. SoC is synthesizable into Altera based FPGA board DE0 Nano. There is also full featured toolchain for programming MARK-II in C.

Whole project is distributed under MIT license except some small parts (vbcc frontend, documentation (licensed under CC)). And is freely available at my github.

Thank you for your interest into MARK-II!

CPU features

  • 32b design
  • 16 registers including 3 special registers
  • Addressing up to 2^{24} words
  • Work up to 50MHz
  • 16 interrupt vectors

Peripherals

  • UARTs - full duplex with configurable baud rate
  • Timers - with interrupts and PWM outputs
  • VGA driver - text mode 80x30 characters with 16 colors
  • PS2 driver - for keyboard
  • GPIO
  • Memories

Toolchain

  • C compiler
  • Some C libraries
  • Assembler
  • Linker
  • Emulator
  • Disassembler
  • Bootloader

refman.pdf

Reference manual for MARK II v1.0.

Adobe Portable Document Format - 466.18 kB - 07/18/2017 at 08:55

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  • 1 × DE0 Nano FPGA kit from Terasic
  • 1 × USB UART converter

  • It works!

    Vladislav Mlejnecký04/13/2018 at 08:07 1 comment

    Today, I was able to load and execute program correctly. Here is a proof:

    But still many work left. I have to double check SDRAM driver, it is seem broken. Take care about others peripherals and test them, rewrite examples and write a lot of documentation.

  • Board!

    Vladislav Mlejnecký03/31/2018 at 17:10 7 comments

    Hurrah! I have almost complete board. One small capacitor is still missing, I'm going to buy it after Easters.

    I chose 0603 size of all passive components. Bad decision. Without hot air soldering station it is pure pain to solder 0603. Some of them are a bit crooked. But it is not so bad as may seem from photo.

    What is on board? Well:

    • MAX 10 FPGA 10M25SA
    • 32MB SDRAM
    • 16Kb I2C FRAM
    • 256Kb SPI NOR SRAM
    • MicroSD slot
    • RTC
    • RS232, PS/2, VGA, 10Mb Ethernet, Audio output
    • Expansion connector

    Next step is run MARK-II on it. It shouldn't be hard. :)

  • SDRAM

    Vladislav Mlejnecký11/20/2017 at 16:05 0 comments

    I just finished SDRAM driver. It is a bit simple driver and is compatible only with IS42S16160B but it is working and now I have plenty of memory space waiting to be filled up with something interesting. :)

    Here is an link to pull request: https://github.com/VladisM/MARK_II/pull/24

    I also made some progress with board. I decided to use MAX10 FPGA. 10M25DAF256 exactly. Yes, in 256pin BGA package . It will a bit challenge to route everything on 4layer board but I will do my best.

  • Linker and libraries

    Vladislav Mlejnecký10/06/2017 at 18:35 0 comments

    I improved linker just now and added ability to link static libraries. It is pretty simple, these static libraries are normal object files generated by assembler. Linker now have new argument for specifying path where to look for such a files. So, when you calling linker and want link static library into your binary, everything what you have to do is give a path, where library is stored, into linker with -l argument.

    Linker try to link your files and if there are missing exported labels (like functions defined in libraries) then linker is going to search libraries paths.

    Creating static library is simple too. Just compile your C code into assembler, and then translate it with assembler into object file.

    I'm also thinking a lot about my bachelor thesis. I'm want to create board for MARK-II that will be fully open sourced. But I can't decide which FPGA to chose. I would like to fit everything into 4 layer PCB, and that can be a bit hard to do with 256pin BGA package that Cyclone IV in DE0 Nano have. So, I'm looking for solution in TQFP package. Unfortunately, Cyclone IV is packed in TQFP and variant with 22K LUT have only 79 IO. That is not enough for SDRAM and all peripherals. Larger TQFP package is available only in Cyclone III family. And unfortunately (again) these devices are available only with low speed grade. I'm wondering about breaking my design into two smaller FPGA (FPGA + CPLD maybe) but that is not way that I want to chose. Does anyone have better idea?


  • New CPU Core

    Vladislav Mlejnecký09/29/2017 at 16:10 0 comments

    I'm happy to announce that new CPU core is successfully tested and merged into master branch!

    I'm worked on the new CPU about three last weeks and finally got it. New CPU bring to MARK-II SoC new features and improve performance in many ways. List of new features:

    • Floating point unit for single precision numbers
    • Improved barrel shifter
    • Fast multiplier and divider
    • Software interrupts
    • Improved internal architecture together with instruction format
    • Improved comparator

    New core is running at 40MHz (a bit slow down compared to old one) but it is able to finish almost all (except divide and floats) instruction in only 3 cycles. First cycle is read from memory, second is instruction decoding and last one is instruction execution. Some instruction are a bit pipelined, and they are finishing while new instruction is read from memory.

    Barrel shifter and condition generator is a bit improved with vbcc in mind, so comparisons in C is a bit faster now. Same about shifting.

    New multiplier is implemented using DPS block in FPGA, so it is really fast and MARK-II is able to multiply two 32bit numbers in one cycle. Macros for multiplication is no longer needed!

    Except CPU, interrupt driver is changed significantly. Now there isn't fixed interrupt vector but you are able to configure address where CPU should jump when interrupt come. This simplify interrupt implementation in C. Simply make pointer to you ISR and store it in interrupt driver registers.

    New CPU is a bit large but it should be good base to start wondering about custom OS. Or port older MINIX maybe? Anyway, I'm in final year at university and I have to start working on my bachelor thesis and I'm pretty sure it will be some nice board for MARK-II with plenty of RAM and many interfaces.

  • SPL examples

    Vladislav Mlejnecký09/11/2017 at 13:27 0 comments

    I just merged branch that bring some examples of using Standard Peripheral Library from C code. You can found these examples at this link.

    There are only three simple examples at now. GPIO, UART and VGA. It is mostly because many features request work with interrupts. But interrupts are not implemented in vbcc backend yet. I will add this feature probably with new CPU core because I'm going to significantly change interrupt mechanism.

    But now, thank to these examples, I was able to chatch many bugs in SPL and even more in compiler backend itself. I also added some more simple optimizations in generated assembly.

  • UART update

    Vladislav Mlejnecký09/01/2017 at 10:40 0 comments

    Today I merged new UART core into SoC. This new core have many benefits over the old one. For example:

    • FIFO buffers for receiver and transmitter
    • Two separated clock domains
    • Better interrupt management

    FIFO buffers are the win. Thanks to them, I can separate system interface from receiver and transmitter. Receiver together with transmitter are still running on 14,4 MHz to simply divide baudrate, but system clock can be raised significantly. At now I'm running at 80MHz without problems.

    I also rewrote loader to work with new UART core, and tested it under emulator and inside of FPGA too.

    New UART core is merged into branch "next" there is link to closed pull request.

  • C Compiler working

    Vladislav Mlejnecký08/22/2017 at 20:50 0 comments

    Today, I compiled simple C program with vbbc and then ran it on MARK-II successfully. So I finally have C compiler for my CPU!

    Of course, there are a lot of bugs and there is plenty of work left, but, it simply works!

    Next goals are:

    • Port some C standard library (newlib?)
    • Write peripheral library
    • Improve CPU architecture to get better performance
    • Find as many bugs as can and eliminate them.

    Code that I ran is really simple:

    #define TIME 0x2FFFF
    static void delay(int time);
    static unsigned int* DDRA = 0x101;
    static unsigned int* PORTA = 0x100;
    int main(){
        *DDRA = 0xFF;
        while(1){
            *PORTA = 0xAA;
            delay(TIME);
            *PORTA = 0x55;
            delay(TIME);
        }
        return 0;
    }
    static void delay(int time){
        unsigned int i;
        for(i = 0; i < time; i = i + 1);
    }
    

    It is hello world with LED. And I had a lot of problems with it. I discovered few bugs in emitting comparison code, I found out that loader isn't working correctly, and I spent a lot of time before I noticed I accidentally swap DDRA and PORTA registers addresses.

    There is also link to commit that add vbcc into my project repository at github.

  • Retargeting C compiler

    Vladislav Mlejnecký08/14/2017 at 17:00 0 comments

    I'm now working on retargeting C compiler. I can say, it is not easy job for me. I tried read something about LCC but LCC seem a bit hard to retarget, not so hard as GCC, but for example vbcc can be retarget more easily.  So I started writing backend for vbcc.

    I'm almost done and things like branching, arithmetic are working well, also global and static variables. But I got stuck at stack related parts, this mean calls to others functions, arguments passing, local variables and so on.

    If somebody can share link where I can find information about how C Compilers are using stack I will be glad.

    Also, it is not clear to me, how to deal with libraries. Have I write my own libraries to be ANSI C compatible? Or is OK to write just backend for vbcc and say "let there be an compiler"? For now I don't want any operating system for my CPU so I suppose, it should be OK to write just backend. 

  • First release

    Vladislav Mlejnecký07/18/2017 at 09:05 0 comments

    Today, I released first release of MARK II. You can clone repository from my GitHub. This first version include:

    • Fully working RISC CPU core with set of simple peripherals
    • Fully working tools like Assembler, Emulator and so on
    • Reference manual for whole SoC

    Now I have some base point for next development. Things that I want to implement next are:

    • Better UART with buffers
    • Faster CPU core
    • SDRAM driver
    • Port of the LCC

    I will be glad for any feedback.

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Discussions

f4hdk wrote 12/21/2017 at 13:45 point

I like it!

Have you seen my A2Z project?

https://hackaday.io/project/18206

The CPU itself is much simpler than yours, but I have developed a fully usable machine with graphics, mass storage, filesystem, etc... Everything is home made, including the language, the compiler, the instruction set, etc...

  Are you sure? yes | no

Vladislav Mlejnecký wrote 12/21/2017 at 14:27 point

Thank you!
Yes, I seen. :) Actually, for a short while, before I ported vbcc, I wondered if is possible to stole your compiler. :D You project is more complex than my. :) For example, I don't have any useful software for my machine yet. (Except some small test progs)

  Are you sure? yes | no

Matt Stock wrote 09/01/2017 at 11:48 point

Nice!  This is very similar to my Bexkat CPU project (also on hackady.io) project.  Looking forward to seeing how this progresses.  Let me know if I can be of assistance.

  Are you sure? yes | no

Vladislav Mlejnecký wrote 09/01/2017 at 13:10 point

Thank you, but your gcc port take your project to another level than my. Good work!

I'm planning something like that:
1) port newlib
2) write C peripheral library
3) improve CPU to get more power
4) try to program something like OS (probably with lua (I always want to try lua))

  Are you sure? yes | no

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