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MARK-II

Simple SoC written in VHDL.

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This is project about creating custom CPU architecture from scratch, including instruction set, programming model and so on.

But CPU is only beginning. There are also some peripherals like timers, uarts, memories (both ROM and RAM), VGA output for monitor, PS2 for input from keyboard...

So, It isn't only CPU, it is whole System on Chip. Whole written with VHDL and synthesizable into DE0 Nano FPGA board.

Also, because without tool is almost impossible to write something useful, I created tools like assembler, linker, emulator everything written in Python.

All source codes, including tools, VHDL codes for SoC are free to download under MIT license at my GitHub page.

CPU features

  • 32b design
  • 16 registers including 3 special registers
  • Addressing up to 2^{24} words
  • Tested up to 50MHz
  • 32 interrupt vectors

Peripherals

  • UARTs - full duplex with configurable baud rate
  • Timers - with interrupts and PWM outputs
  • VGA driver - text mode 80x30 characters with 16 colors
  • PS2 driver - for keyboard
  • GPIO
  • Memories

Tools

  • Assembler
  • Linker
  • Emulator
  • Disassembler
  • Bootloader
  • some others scripts

refman.pdf

Reference manual for MARK II v1.0.

Adobe Portable Document Format - 466.18 kB - 07/18/2017 at 08:55

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  • 1 × DE0 Nano FPGA kit from Terasic
  • 1 × USB UART converter

  • First release

    Vladislav Mlejnecký5 days ago 0 comments

    Today, I released first release of MARK II. You can clone repository from my GitHub. This first version include:

    • Fully working RISC CPU core with set of simple peripherals
    • Fully working tools like Assembler, Emulator and so on
    • Reference manual for whole SoC

    Now I have some base point for next development. Things that I want to implement next are:

    • Better UART with buffers
    • Faster CPU core
    • SDRAM driver
    • Port of the LCC

    I will be glad for any feedback.

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