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• I'm still breathing!

  Vladislav Mlejnecký • 06/28/2019 at 08:56 • 0 comments

  Hello!

  I had to check that date twice, but my last log is half year old ... well ... I writing this log just to say that I'm not death. I'm still breathing! :D

  A few last months brings interesting news. In short, I lost GF, quit school, started working at full time, disconnect myself from internet (since first of June), have injury at Aikido, started with Kenjutsu, bought ukulele, started again with piano. Now I'm looking for new flat. :) 

  But nothing can stop me in order to create ultimate CPU like MARK-II is! :D I finished assembler, it should be relatively easy to port for another architecture. In same way (easy to port with changing only one library), I'm working on rest of toolchain, so linker, archiver and supporting utilities.
  

  I didn't have estimate when I will finish it. I have prepared book about linkers but not started reading it yet. When toolchain will be completed, I'm going to update CPU architecture, remove useless parts like FPU, and increase speed.
  

  But as I spend all day programming in my work, I simply doesn't have too much willpower to program at home too. So ... I don't know how long it will take.
  
  

• Still here :)

  Vladislav Mlejnecký • 12/04/2018 at 10:03 • 0 comments

  Hi!

  In my last log I said that I'm still working on MARK-II. That is true, but it seems like I was a bit optimistic in time estimating. It will not take a few month, rather a few years.

  I moved to new flat, and start living together with my girlfriend. I also started studying another school and started practicing Aikido. So not too much free time left for programming. :)

  Anyway, I'm still working on this project. Here is small proof. This is almost finished assembler rewriten to C.
  

  This also should bring new features like addressing individual bytes, and add program sections.
  

• Small update

  Vladislav Mlejnecký • 07/20/2018 at 10:13 • 0 comments

  Hi!

  this log will be really short. I finished my school.... get new job as embedded developer ... and didn't have too much free time left.

  Anyway, I'm still working on this project. And don't want stop it. At this time I'm working on toolchain update, I want to rewrite it to C and make some things faster, especially bootloader.

  I also want to start work on stdlibc, I'm in touch with vbcc author, Dr. Berthelmann, and ask him about more information about vclib.

  And of course ... I want write rest of peripherals, and improve CPU performance, maybe using pipeline. :) 

  All these goals will probably take about few month to complete, maybe even year. So wish me luck!
  

• It works!

  Vladislav Mlejnecký • 04/13/2018 at 08:07 • 3 comments

  Today, I was able to load and execute program correctly. Here is a proof:
  

  But still many work left. I have to double check SDRAM driver, it is seem broken. Take care about others peripherals and test them, rewrite examples and write a lot of documentation.

• Board!

  Vladislav Mlejnecký • 03/31/2018 at 17:10 • 7 comments

  Hurrah! I have almost complete board. One small capacitor is still missing, I'm going to buy it after Easters.
  

  I chose 0603 size of all passive components. Bad decision. Without hot air soldering station it is pure pain to solder 0603. Some of them are a bit crooked. But it is not so bad as may seem from photo.

  What is on board? Well:

  • MAX 10 FPGA 10M25SA
  • 32MB SDRAM
  • 16Kb I2C FRAM
  • 256Kb SPI NOR SRAM
  • MicroSD slot
  • RTC
  • RS232, PS/2, VGA, 10Mb Ethernet, Audio output
  • Expansion connector

  Next step is run MARK-II on it. It shouldn't be hard. :)

• SDRAM

  Vladislav Mlejnecký • 11/20/2017 at 16:05 • 0 comments

  I just finished SDRAM driver. It is a bit simple driver and is compatible only with IS42S16160B but it is working and now I have plenty of memory space waiting to be filled up with something interesting. :)
  
  Here is an link to pull request: https://github.com/VladisM/MARK_II/pull/24
  
  I also made some progress with board. I decided to use MAX10 FPGA. 10M25DAF256 exactly. Yes, in 256pin BGA package . It will a bit challenge to route everything on 4layer board but I will do my best.
  

• Linker and libraries

  Vladislav Mlejnecký • 10/06/2017 at 18:35 • 0 comments

  I improved linker just now and added ability to link static libraries. It is pretty simple, these static libraries are normal object files generated by assembler. Linker now have new argument for specifying path where to look for such a files. So, when you calling linker and want link static library into your binary, everything what you have to do is give a path, where library is stored, into linker with -l argument.

  Linker try to link your files and if there are missing exported labels (like functions defined in libraries) then linker is going to search libraries paths.

  Creating static library is simple too. Just compile your C code into assembler, and then translate it with assembler into object file.

  I'm also thinking a lot about my bachelor thesis. I'm want to create board for MARK-II that will be fully open sourced. But I can't decide which FPGA to chose. I would like to fit everything into 4 layer PCB, and that can be a bit hard to do with 256pin BGA package that Cyclone IV in DE0 Nano have. So, I'm looking for solution in TQFP package. Unfortunately, Cyclone IV is packed in TQFP and variant with 22K LUT have only 79 IO. That is not enough for SDRAM and all peripherals. Larger TQFP package is available only in Cyclone III family. And unfortunately (again) these devices are available only with low speed grade. I'm wondering about breaking my design into two smaller FPGA (FPGA + CPLD maybe) but that is not way that I want to chose. Does anyone have better idea?

  
  

• New CPU Core

  Vladislav Mlejnecký • 09/29/2017 at 16:10 • 0 comments

  I'm happy to announce that new CPU core is successfully tested and merged into master branch!

  I'm worked on the new CPU about three last weeks and finally got it. New CPU bring to MARK-II SoC new features and improve performance in many ways. List of new features:

  • Floating point unit for single precision numbers
  • Improved barrel shifter
  • Fast multiplier and divider
  • Software interrupts
  • Improved internal architecture together with instruction format
  • Improved comparator

  New core is running at 40MHz (a bit slow down compared to old one) but it is able to finish almost all (except divide and floats) instruction in only 3 cycles. First cycle is read from memory, second is instruction decoding and last one is instruction execution. Some instruction are a bit pipelined, and they are finishing while new instruction is read from memory.

  Barrel shifter and condition generator is a bit improved with vbcc in mind, so comparisons in C is a bit faster now. Same about shifting.
  

  New multiplier is implemented using DPS block in FPGA, so it is really fast and MARK-II is able to multiply two 32bit numbers in one cycle. Macros for multiplication is no longer needed!
  

  Except CPU, interrupt driver is changed significantly. Now there isn't fixed interrupt vector but you are able to configure address where CPU should jump when interrupt come. This simplify interrupt implementation in C. Simply make pointer to you ISR and store it in interrupt driver registers.

  New CPU is a bit large but it should be good base to start wondering about custom OS. Or port older MINIX maybe? Anyway, I'm in final year at university and I have to start working on my bachelor thesis and I'm pretty sure it will be some nice board for MARK-II with plenty of RAM and many interfaces.
  
  

• SPL examples

  Vladislav Mlejnecký • 09/11/2017 at 13:27 • 0 comments

  I just merged branch that bring some examples of using Standard Peripheral Library from C code. You can found these examples at this link.
  

  There are only three simple examples at now. GPIO, UART and VGA. It is mostly because many features request work with interrupts. But interrupts are not implemented in vbcc backend yet. I will add this feature probably with new CPU core because I'm going to significantly change interrupt mechanism.

  But now, thank to these examples, I was able to chatch many bugs in SPL and even more in compiler backend itself. I also added some more simple optimizations in generated assembly.
  
  

• UART update

  Vladislav Mlejnecký • 09/01/2017 at 10:40 • 0 comments

  Today I merged new UART core into SoC. This new core have many benefits over the old one. For example:

  • FIFO buffers for receiver and transmitter
  • Two separated clock domains
  • Better interrupt management

  FIFO buffers are the win. Thanks to them, I can separate system interface from receiver and transmitter. Receiver together with transmitter are still running on 14,4 MHz to simply divide baudrate, but system clock can be raised significantly. At now I'm running at 80MHz without problems.

  I also rewrote loader to work with new UART core, and tested it under emulator and inside of FPGA too.

  New UART core is merged into branch "next" there is link to closed pull request.
  

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