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A project log for MARK-II

Simple SoC written in VHDL.

Vladislav MlejneckýVladislav Mlejnecký 03/31/2018 at 17:107 Comments

Hurrah! I have almost complete board. One small capacitor is still missing, I'm going to buy it after Easters.

I chose 0603 size of all passive components. Bad decision. Without hot air soldering station it is pure pain to solder 0603. Some of them are a bit crooked. But it is not so bad as may seem from photo.

What is on board? Well:

Next step is run MARK-II on it. It shouldn't be hard. :)

Discussions

Martin Cejp wrote 04/08/2018 at 09:46 point

It looks great. MAX 10 is a lovely chip.

How many layers did you use for the board?

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Vladislav Mlejnecký wrote 04/08/2018 at 10:06 point

It is four layer board. I designed it against OSH Park rules, so one can order them there.

MAX 10 is great FPGA, but only one PLL can be limitation. Also, if you want use integrated ADC, almost half of pins are unusable. Anyway, they are cheap and powerful enough.

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Martin Cejp wrote 04/08/2018 at 10:11 point

Neat. I'm working with a 10M16SCE144 at the moment, and I am trying to fit into 2 layers. Because I'm not using any of the analog features, and don't need low jitter on PLL, it should be fairly easy.

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Wenting Zhang wrote 04/07/2018 at 22:43 point

The board looks really nice!

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Vladislav Mlejnecký wrote 04/08/2018 at 08:33 point

Thank you! I cleaned it once again using isopropyl and now it looks a bit better. :)


There is new photo https://user-images.githubusercontent.com/17781503/38455173-8274c1d6-3a74-11e8-95c2-0bc5e3296400.jpg

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f4hdk wrote 04/01/2018 at 14:31 point

Beautifull!

But I don't see mass storage on this board... no SD-Card? No flash?

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Vladislav Mlejnecký wrote 04/01/2018 at 15:21 point

I forgotten. There is an SD slot under board.

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