New CPU Core

A project log for MARK-II

Simple SoC written in VHDL.

Vladislav MlejneckýVladislav Mlejnecký 09/29/2017 at 16:100 Comments

I'm happy to announce that new CPU core is successfully tested and merged into master branch!

I'm worked on the new CPU about three last weeks and finally got it. New CPU bring to MARK-II SoC new features and improve performance in many ways. List of new features:

New core is running at 40MHz (a bit slow down compared to old one) but it is able to finish almost all (except divide and floats) instruction in only 3 cycles. First cycle is read from memory, second is instruction decoding and last one is instruction execution. Some instruction are a bit pipelined, and they are finishing while new instruction is read from memory.

Barrel shifter and condition generator is a bit improved with vbcc in mind, so comparisons in C is a bit faster now. Same about shifting.

New multiplier is implemented using DPS block in FPGA, so it is really fast and MARK-II is able to multiply two 32bit numbers in one cycle. Macros for multiplication is no longer needed!

Except CPU, interrupt driver is changed significantly. Now there isn't fixed interrupt vector but you are able to configure address where CPU should jump when interrupt come. This simplify interrupt implementation in C. Simply make pointer to you ISR and store it in interrupt driver registers.

New CPU is a bit large but it should be good base to start wondering about custom OS. Or port older MINIX maybe? Anyway, I'm in final year at university and I have to start working on my bachelor thesis and I'm pretty sure it will be some nice board for MARK-II with plenty of RAM and many interfaces.