As was stated in previous log, I plan to build model register system, which is next level of complexity, as it is will have addressable registers and also less controls compared to previous system (7 vs 8). Here is schematics for it:

There is no option in this system where bus can float, as it always has one of the tri-state outputs open (exactly what output is open is dictated by 2-bit address, first two spdt switches). This model also have global reset, but each register can be set individually via 2-bit address (last two spdt switches), or written to using the same address.

Well, now I have to make it in hardware!