The next step is to detect the startbits of each character. It turned out to be surprisingly simple. Really nothing more than two monostables and two edge detectors is required.

The FSK Demodulator block is the one from the previous posts. It outputs a serial data stream looking like the output from a regular UART. The datastream is idling at high level so when the startbit comes is will have a falling edge. This edge is detected by C2/Q4 and is triggering the first monostable that is set to have a timeout 1.66ms (half a bit period) so the output of this will have a falling edge at the midpoint of the startbit.

Being the midpoint is important since we really want to take the samples of the databits at the middle of each bit-slot in case the clocks are a bit slow or fast.

So this falling edge at the midpoint of the startbit is once more edge detected and is sent out as a short pulse as our startbit-marker in the circuit.

This pulse is also triggering a second monostable with a timeout of 42.5 milliseconds giving an inhibit signal lasting into the stopbits of the current byte. This signal will block any more falling edges during the databits to retrigger the first monoflop that would cause false extra startbits.

Here the red is the incoming serial data. At the same time the blue inhibit line goes high theres a green narrow (almost invisible) pulse signalling the middle of the startbit. This is followed by 8 alternating databits whose edgeds are blocked by the inhibit line (blue). A bit into the two stopbits the inhibit is deactivated making the circuit ready to to detect the next startbit.