I now need to make eight pulses that coincides with the middle of each data bit so I can latch, or just temporarily store, the databits as they pass by. 

First i tried a version with making a 3-bit binary counter out of T-flip flops and decode their Q's and /Q's from binary into separate output with a diode matrix.  This ended up a bit glitchy and requiring a lot of parts.

So I went with a ring counter instead. It's not as "digital" as a binary counter and a decoder but it gets the job done with a decent amount of parts.

I realised that I really don't need the 42ms monoflop that was used to inhibit the startbit detection during the reception of the databits so I removed that an replaced it with an edge triggered SR flipflop that is set by the startbit and reset by the last stage of the ring counter.

The baudrate generator is (re-)started and synchronized when the SR flip flop is set so the issue of having the clock drifting in comparison to the incoming data is reduced.

So now I've got a device that outputs 8 pulses in sync with the actual databits.

The screenshot below shows three bytes of data (0x55, 0xAA and 0x18). To test the synchronization logic the third byte is slightly delayed.

The green trace is the serial stream as output by the FSK demodulator. The cyan pulses are artificially made timing indicators to show where the middle of each data bit are. The red trace is the output of the second stage of the ring counter.