FPGA Simulates Analog Computer

Analog computers are completely parallel. FPGA simulation of analog components implements fast, parallel solution of differential equations.

Description

Traditionally, analog computers use operational amplifiers to implement addition, subtraction and to compute time-integrals of functions. Multiplication was handled by analog multipliers. All of these operations are easy to perform on the FPGA, except for computing time integrals. However, around the time that digital circuitry was getting faster then analog computation, a device called a Digital Differential Analyzer (DDA) was invented to simulate the integral function digitally. I used a version of the DDA which was easy to implement on the FPGA and which gives speedy parallel execution.

Details

The general approach using DDAs will be to simulate a system of first-order differential equations, which can be nonlinear. Analog computers use operational amplifiers to do mathematical integration. We will use digital summers and registers. For any set of differential equations with state variables v1 to vm:  dv1/dt = f1(t,v1,v2,v3,...vm) dv2/dt = f2(t,v1,v2,v3,...vm) dv3/dt = f3(t,v1,v2,v3,...vm)
...
dvm/dt = fm(...)

We will build the following circuitry to perform an Euler integration approximation to these equations in the form

v1(n+1) = v1(n) + dt*(f1(t,v1(n),v2(n),v3(n),...vm(n)) v2(n+1) = v2(n) + dt*(f2(t,v1(n),v2(n),v3(n),...vm(n)) v3(n+1) = v3(n) + dt*(f3(t,v1(n),v2(n),v3(n),...vm(n)) ... vm(n+1) = vm(n) + dt*(fm(...))

Where the variable values at time step n are updated to form the values at time step n+1. Each equation will require one integrator. The multiply may be replaced by a shift-right if dt is chosen to be a power of two. Most of the design complexity will be in calculatingF(t,V(n)).

We also need a number representation. I chose 18-bit 2's complement with the binary point between bits 15 and 16 (with bit zero being the least significant). Bit 17 is the sign bit. The number range is thus -2.0 to +1.999985. This range fits well with the Altera DE2 Audio codec which requires 16-bit 2's complement for output to the DAC. Conversion from the 18-bit to 16-bit just requires truncating the least significant two bits ([1:0]).

Second order system (damped spring-mass oscillator):
As an example, consider the linear, second-order differential equation resulting from a damped spring-mass system:

d2x/dt2 = -k/m*x-d/m*(dx/dt)

where k is the spring constant, d the damping coefficient, m the mass, and x the displacement. We will simulate this by converting the second-order system into a coupled first-order system. If we let v1=x and v2=dx/dt then the second order equation is equivalent to

 <code>dv1/dt = v2 dv2/dt = -k/m*v1-d/m*v2 

These equations can be solved by wiring together two integrators, two multipliers and an adder as shown below. In the past this would have been done by using operational amplifiers to compute each mathematical operation. Each integrator must be supplied with an initial condition.

<code> <code> <img src="http://people.ece.cornell.edu/land/courses/ece5760/DDA/AnalogSim2order/SecondOrder.png" height="133" width="434"> 

Converting this diagram to Verilog, the top-level module verilog code defines the 18-bit, signed, state variables and a clock divider variable (count). The clocked section resets and updates the state variables. The combinatorial statements compute the Euler approximation to the F(t,V(n)). The separate multiply module ensures that the multiplies will be instantiated as hardware multipliers. The Audio_DAC_ADC module was modifed to allow either ADC-to-DAC passthru or to connect the computation output to the DAC, depending on the position of SW17. SW17 up connects the computation.

All details at

http://people.ece.cornell.edu/land/courses/ece5760/DDA/index.htm

<code><code>

Discussions

Ken Pack wrote 01/16/2017 at 16:41

Can you explain the advantage of using the DDA to model a non-linear system?
Stepping back for a moment from FPGA implementations, I thought that any
non-linear system, could be modeled to fit an LTI system.

Let us imagine for a moment the steady state system begins to oscillate, can a DDA ever become deterministic? The sources for the DDA models are very academic.

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Bruce Land wrote 03/12/2016 at 13:00

What code are you talking about.? You just copied back the integrator code, but not the rest of the DDA.

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shrivardhan2011 wrote 03/12/2016 at 07:20

this code runs and compiles sucessfully. But is this what we call DDA?

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shrivardhan2011 wrote 03/12/2016 at 07:20

alright so u have the code module integrator(out,funct,InitialOut,dt,clk,reset);

output [17:0] out; //the state variable V
input signed [17:0] funct; //the dV/dt function
input [3:0] dt ; // in units of SHIFT-right
input clk, reset;
input signed [17:0] InitialOut; //the initial state variable V

wire signed [17:0] out, v1new ;
reg signed [17:0] v1 ;

always @ (posedge clk)
begin
if (reset==0) //reset
v1 <= InitialOut ; //
else
v1 <= v1new ;
end
assign v1new = v1 + (funct>>>dt) ;
assign out = v1 ;
endmodule

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shrivardhan2011 wrote 03/11/2016 at 16:40

is this the code

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Bruce Land wrote 03/11/2016 at 19:09

this is a very specific dynamic system. I assume you are interested in the more general code, which is why I suggested the last code on http://people.ece.cornell.edu/land/courses/ece5760/DDA/index.htm

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shrivardhan2011 wrote 03/11/2016 at 16:39

module Iz_neuron(out,spike,a,b,c,d,I,clk,reset);

output [17:0] out;
output spike ;
input signed [17:0] a, b, c, d, I;
input clk, reset;

wire signed [17:0] out;
reg spike;
reg signed [17:0] v1,u1;
wire signed [17:0] u1reset, v1new, u1new, du1;
wire signed [17:0] v1xv1, v1xb;
wire signed [17:0] p, c14;

assign p = 18'sh0_4CCC ; // 0.30
assign c14 = 18'sh1_6666; // 1.4

assign out = v1; //copy state var to output

always @ (posedge clk)
begin
if (reset)
begin
v1 <= 18'sh3_4CCD ; // -0.7
u1 <= 18'sh3_CCCD ; // -0.2
spike <= 0;
end
else
begin
if ((v1 > p))
begin
v1 <= c ;
u1 <= u1reset ;
spike <= 1;
end
else
begin
v1 <= v1new ;
u1 <= u1new ;
spike <= 0;
end
end
end

// dt = 1/16 or 2>>4
// v1(n+1) = v1(n) + dt*(4*(v1(n)^2) + 5*v1(n) +1.40 - u1(n) + I)
// but note that what is actually coded is
// v1(n+1) = v1(n) + (v1(n)^2) + 5/4*v1(n) +1.40/4 - u1(n)/4 + I/4)/4
signed_mult v1sq(v1xv1, v1, v1);
assign v1new = v1 + ((v1xv1 + v1+(v1>>>2) + (c14>>>2) - (u1>>>2) + (I>>>2))>>>2);

// u1(n+1) = u1 + dt*a*(b*v1(n) - u1(n))
signed_mult bb(v1xb, v1, b);
signed_mult aa(du1, (v1xb-u1), a);
assign u1new = u1 + (du1>>>4) ;
assign u1reset = u1 + d ;
endmodule

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shrivardhan2011 wrote 03/10/2016 at 19:01

Can you share your email id where I will send the code which i have currently with me?

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Bruce Land wrote 03/10/2016 at 19:19

I cannot debug your code.

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shrivardhan2011 wrote 03/10/2016 at 18:58

Christ,First of all I am confused there are several codes out of which I am not able to identify. Can you tell how to access your code on this page. From where on this page I will get the code?

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Bruce Land wrote 03/10/2016 at 19:20

I liked the very last version on the page.

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shrivardhan2011 wrote 03/10/2016 at 18:16

my project is on Verilog Quartus and FPGA used is Altera Cyclone II

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Bruce Land wrote 03/10/2016 at 18:47

That is the platform I used with the code on the page. What errors are you getting?

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shrivardhan2011 wrote 03/10/2016 at 17:50

Please do need full I have to submit my project on monday. My topic is to simulate DDA on verilog HDL

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shrivardhan2011 wrote 03/10/2016 at 17:49

I tried but getting errors and so i also visited the site http://people.ece.cornell.edu/land/courses/ece5760/DDA/index.htm but got many codes and all show errors while compilation

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Bruce Land wrote 03/10/2016 at 18:12

What software? what FPGA?

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Bruce Land wrote 03/10/2016 at 16:52

It is on the page

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shrivardhan2011 wrote 03/10/2016 at 16:47

Please can you send me the verilog code file to shrivardhan2011@hotmail.com

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FPGA Simulates Analog Computer

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