The general approach using DDAs will be to simulate a system of first-order differential equations, which can be nonlinear. Analog computers use operational amplifiers to do mathematical integration. We will use digital summers and registers. For any set of differential equations with state variables `v1` to `vm`: ```<br> <br> dv1/dt = f1(t,v1,v2,v3,...vm) <br> dv2/dt = f2(t,v1,v2,v3,...vm)<br> dv3/dt = f3(t,v1,v2,v3,...vm)```
...
`dvm/dt = fm(...) `

We will build the following circuitry to perform an Euler integration approximation to these equations in the form

```v1(n+1) = v1(n) + dt*(f1(t,v1(n),v2(n),v3(n),...vm(n))<br> v2(n+1) = v2(n) + dt*(f2(t,v1(n),v2(n),v3(n),...vm(n))<br> v3(n+1) = v3(n) + dt*(f3(t,v1(n),v2(n),v3(n),...vm(n))<br> ...<br> vm(n+1) = vm(n) + dt*(fm(...))```

``` ```

Where the variable values at time step `n` are updated to form the values at time step `n+1`. Each equation will require one integrator. The multiply may be replaced by a shift-right if `dt` is chosen to be a power of two. Most of the design complexity will be in calculating`F(t,V(n))`.

We also need a number representation. I chose 18-bit 2's complement with the binary point between bits 15 and 16 (with bit zero being the least significant). Bit 17 is the sign bit. The number range is thus `-2.0` to `+1.999985`. This range fits well with the Altera DE2 Audio codec which requires 16-bit 2's complement for output to the DAC. Conversion from the 18-bit to 16-bit just requires truncating the least significant two bits ([1:0]).

Second order system (damped spring-mass oscillator):
As an example, consider the linear, second-order differential equation resulting from a damped spring-mass system:

`d<sup>2</sup>x/dt<sup>2</sup> = -k/m*x-d/m*(dx/dt)`

``` ```

where k is the spring constant, d the damping coefficient, m the mass, and x the displacement. We will simulate this by converting the second-order system into a coupled first-order system. If we let `v1=x` and` v2=dx/dt` then the second order equation is equivalent to

```<br> <br> <code>dv1/dt = v2<br> dv2/dt = -k/m*v1-d/m*v2<br> ```

These equations can be solved by wiring together two integrators, two multipliers and an adder as shown below. In the past this would have been done by using operational amplifiers to compute each mathematical operation. Each integrator must be supplied with an initial condition.

```<code> <code><br> <img src="http://people.ece.cornell.edu/land/courses/ece5760/DDA/AnalogSim2order/SecondOrder.png" height="133" width="434"><br> <br> ```

Converting this diagram to Verilog, the top-level module verilog code defines the 18-bit, signed, state variables and a clock divider variable (`count`). The clocked section resets and updates the state variables. The combinatorial statements compute the Euler approximation to the `F(t,V(n))`. The separate multiply module ensures that the multiplies will be instantiated as hardware multipliers. The Audio_DAC_ADC module was modifed to allow either ADC-to-DAC passthru or to connect the computation output to the DAC, depending on the position of SW17. SW17 up connects the computation.

All details at

http://people.ece.cornell.edu/land/courses/ece5760/DDA/index.htm

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