SNES Gamepad FPGA Module

Verilog module to read SNES gamepad status.

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This module reads the status of the buttons on a SNES gamepad. The user interacts with the module via three signals:

* rd
* busy
* buttons

The *rd* signal is used to command the module to begin the read operation. The *busy* signal is active high when the module is executing a read. Lastly, the *buttons* signal contains the status of the SNES buttons at the completion of the read.

The module interacts with the SNES controller via three signals:

* snes_latch
* snes_clk
* snes_data

The read process is initiated by holding the *snes_latch* signal high for 12 us. At the end of the *snes_latch* signal, the first button status (B) is available on *snes_data* and the *snes_clk* cycles through sixteen rising edge transitions with a 12 us clock period. The *snes_data* signal is read on the falling edge of *snes_clk*. The *snes_data* signal is active low and the module inverts the result.

Video Aug 20, 16 06

Video of SNES controller and the FPGA module with the Nexys 4 DDR board.

quicktime - 32.85 MB - 08/20/2017 at 20:14


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Luke Valenty wrote 08/20/2017 at 14:34 point

Pretty cool.  Do you have to debounce the buttons or is that taken care of in the SNES controller itself?  Have you integrated this into a larger project?

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Ryan wrote 08/20/2017 at 14:41 point

Great question. You don't have to debounce the buttons because inside the SNES controller are two 8-stage shift registers in parallel for the 12 buttons. The latch signal latches the button status into the shift registers and the clock cycles them through the data signal. I'll post some more information on that, thanks for bringing that up!

As for a larger project, not yet. I've hooked this up to the Nexus 4 DDR board, I'll post a video or photo of it in action. I'd like to work this into something like a Pong game or other simple game to display via VGA.

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Luke Valenty wrote 08/20/2017 at 16:28 point

A simple game implemented in verilog would be slick.

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