In this log, the first renders of the pcb layout are presented and a major change in the design.
First off, the change was that we changed the FPGA package as obviously the 484 pin was an overkill for this design. The package was switched for the 256 pin BGA that shaves off a little bit form the chip cost and saves us the unnecessary layers that the 484 would require to escape the BGA.
In the picture above we can see the functions of the board. The user would simply wire up the master and slave interfaces required and provide a 5V supply either by plugpack or the two dedicated pins next to the jack input. The device then will handle the communication between these devices regardless of the protocol used by each one.
The top LEDs and two buttons have mainly debugging purposes, while they could be informative for the user they do not provide any function for the main purpose of the board. As for the configuration of the board a JTAG header is used in standard SPI flash mode, in the future a usb interface is planned to provide the user a more streamlined interface for the dynamic reconfiguration of the FPGA.
Evidently the board could be made a lot denser if the 2.54mm headers in this layout would allow, however for this prototype we kept to the original plan of a 10x10 cm board.
The board uses a 6 layer stackup where:
- Top is mixed power & signals
- Ground layer
- Signal layer
- Signal Layer
- Ground layer
- Power layer
The layout was pretty straight forward as there are no particularly high-speed signals or differential pairs for our interfaces. Probably the most intense part of the layout was getting the BGA fanout and getting the power planes to reach the FPGA as all 3 power rails use the bottom layer to get there. For that reason, the bypass capacitors of the FPGA were placed on the bottom as placing them on top would result in a bigger loop.
There is a lot of work still to be done before going on with manufacturing, for once the design and layout must be quadruple checked, the silkscreen markings and the general aesthetic presentation of the board must be designed and at least some spice simulations, mainly on the SPI clock signal traces must run to verify the signal quality.
The new schematic pdf file along with a pdf of the layout plots will be uploaded here, and of course the whole project can be found on GitHub.