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Chips4Makers Pilot: Retro-uC

Chips want to be free

Staf VerhaegenStaf Verhaegen
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  • Staf VerhaegenStaf Verhaegen

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  • gitlab
  • crowdsupply
  • Slides ORConf 2017
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ongoing project
open source silicon RETRO

This project was created on 09/02/2017 and last updated 2 years ago.

Description

I am working on a project for an open source ASIC implemented with an open source EDA flow. This is a pilot project with long term goal to provide makers the possibility to make their own chips. For the pilot some classic CPUs from the nineties with an open source implementation will be used for a micro-controller. The project was presented at ORConf 2017; you can find the slides in the external links.

Project Logs
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  • Mixed RTL language open source flow

    Staf Verhaegen • 01/06/2020 at 19:10 • 0 comments

    It's been a long time I put something here and my promise for this year is to be more active. I have been working quietly on the Chips4Makers low-volume manufacturer flow.

    My most recent success is to have replaced the proprietary Verific plugin for Yosys to do synthesis on VHDL code with the open source ghdlsynth-beta from Tristan Gingold.

    More details can be found in my blog post.

  • The Retro-uC is death - long live the Retro-uC !

    Staf Verhaegen • 11/25/2018 at 14:05 • 0 comments

    People who follow my project will have noticed that the crowdfunding campaign has come to an end. Unfortunately it did not reach it funding goal. Fortunately this does not mean the end (yet) for the Retro-uC and the Chips4Makers projects.

    More details can be found in my latest blog post.

  • First time right - yes, we can !

    Staf Verhaegen • 09/15/2018 at 16:56 • 0 comments

    I posted a new blog post on another 'common wisdom' that would be violated by my project; e.g. that you need at least two iterations to get a working chip.

    Enjoy!.

  • Startup costs and low volume manufacturing

    Staf Verhaegen • 09/02/2018 at 21:31 • 0 comments

    Inspired by the comment on social media on the launch of the Retro-uc crowdfunding campaign I posted a blog on startup costs and the choices made for the Retro-uC in order to reach a low funding goal.

  • Retro-uC campaign live on crowdsupply

    Staf Verhaegen • 08/23/2018 at 20:20 • 0 comments

    The Retro-uC campaign is now live on crowdsupply.

    So the time has come you can show your support for this project and for the silicon movement.

    If you like it, please spread the word!

  • Motorola 68000 support ready in Retro-uC

    Staf Verhaegen • 06/18/2018 at 21:24 • 1 comment

    The Motorola 68000 support in the Retro-uC has been finished. More details can be found in my blog post; the release can be found on gitlab.

    If there people who fancy porting the Retro-uC to another FPGA, don't hesitate to contact me.

  • Retro-uC Blink Demo on XLR8

    Staf Verhaegen • 05/01/2018 at 14:10 • 0 comments

    I made a video of a demo of the Retor-uC running on the Alorium XLR8 FPGA board. Please find all details in a blog post on the chipsmakers.io blog.

    I am interested to know what you think, so don't hesitate to comment here.

  • Retro-uC Crowdfunding Campaign Product Options

    Staf Verhaegen • 01/31/2018 at 19:41 • 0 comments

    The technical stuff seems to finally converge to a phase that launching of the Retro-uC campaign is getting close. In the current state four product options are planned: a chip, a breadboardable board, a prototyping board and a stand-alone board with Arduino MEGA IO layout.

    The details are given in my latest blog post. All feedback and suggestions for improvement are welcome here. Do realise I may only be able to reply when I'm back from FOSDEM next weekend.

  • 34C3 inspiration and buzzwords pt. 3

    Staf Verhaegen • 01/02/2018 at 22:24 • 0 comments

    Inspired by the vibe I felt at the 34C3 conference I wrote my third part of the buzzwords article.

    I really hope to be able to report more technical things in the short term but I am focusing currently on getting the production flow ready and discussions are going slow. Some changes should pup op on the gitlab repository in the coming days/weeks.

  • The importance of crowdfunding

    Staf Verhaegen • 11/26/2017 at 15:21 • 0 comments

    In my second part of the buzzwords article for this project I am discussing crowdfunding and why I think it is an important piece of the puzzle for low-volume open silicon.

    It's also mentioned in the article that currently I am busy discussing the cost and the flow of the production run before officially launching the campaign. When this is finished I will be able to share more public information.

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prosto wrote 10/27/2018 at 12:17 • point

I need all working device for example https://www.kickstarter.com/projects/954662076/gameshell-redefine-retro-game-console

in my opinion great will be this procesor AND FPGA (like epiphany parallela) for future function

  Are you sure? yes | no

Staf Verhaegen wrote 10/27/2018 at 12:33 • point

As my Retro-uC did not reach the funding goal currently no chips will be produced until I can relaunch a new compaign that reaches it's goal.

For FPGA retro-boards you can look at the FPGA Arcade (https://www.fpgaarcade.com/) and Mist (http://www.harbaum.org/till/mist/index.shtml) communities

  Are you sure? yes | no

prosto wrote 11/11/2018 at 15:15 • point

2 processor is better then one. ask nasa (every mission have more different processor)

  Are you sure? yes | no

hlide wrote 09/05/2018 at 09:52 • point

Again I like very much the idea. However, there are major flaws which prevent me from backing it. The price ($42+$8+possible toll taxes) and some features are lacking:
- 3 cores but only one active for this price? I would rather take the genuine one.
- no bus for external storage? I would rather take the genuine one.
- speed less than 10MHz?  I would rather take the genuine one (Z80: 20MHz, M68K: 25MHz).
I don't see what I can do with it.  

  Are you sure? yes | no

Julian wrote 09/05/2018 at 11:39 • point

This is a good point ... No external memory bus means you can't do anything with it that demands attaching devices that either directly access memory or are themselves memory mapped.  No graphical output (maybe you can make something text mode work, but bitmapped would be a huge issue), no high speed storage.  You won't be able to make any standard OSs for any of the cores run, and the performance will be significantly worse than am AVR or PIC, which are about the only comparable modern architectures (although I wonder where the figure of 10MHz comes from ... simply implementing the simplest possible design for each core on a .35um process ought to result in much better speed than that; at that size I'd have hoped to see at least 30MHz for a Z80 core, although slightly less for the others as they do more per cycle).

Frankly, just using an FPGA would be easier and cheaper. And if open source design is important to you, there are RISCV systems available that tick that box.

  Are you sure? yes | no

hlide wrote 09/05/2018 at 16:35 • point

The author answered it would be probably under 10MHz in a comment of the hackaday.io article. However, he never answered to my questions (the same as I posted here) - I asked through a CrowdSupply message and the article comments. So I decided to post here... We'll see whether his project reach the goal.

  Are you sure? yes | no

Staf Verhaegen wrote 09/05/2018 at 19:05 • point

This is a low volume ASIC so the price is what it is. It will never be able to compete with proprietary, high volume chips. So it's up to you if like the Retro-uC enough to want to spend that money. It still does not cost an arm and a leg.

Originally I planned to have a different version for each core but it was easier to combine them on one chip without increased cost. On-chip RAM is big part of the cost.

I did go for microcontroller version of the chip with big number of I/O and not for microprocessor as these are indeed readily available.

I am going to look if I can implement an external SRAM interface that can optionally be enabled. But only when I have tested it successfully and I consider the risk on having a killer bug introduced in the chip minimal, I will add it to the chip.

In general I tried to limit the amount of features as each feature risks introducing a bug and if it is means the chip does not work all backers will loose their money.

I think I replied to reach speed above 10MHz. How far above needs to still be determined, I hope to be able to announce that before end of campaign.

PS: I did reply to your question asked through the campaign page so it seems to not have gone through your SPAM filter.

  Are you sure? yes | no

hlide wrote 09/05/2018 at 21:21 • point

Thanks. Since you answered here, let us forget about the reply which might have not gone through my SPAM filter. Fine, I certainly mis-interpreted the 10MHz reach speed. I'm glad to hear your thinking about implementing an optional external SRAM interface for those needing one even if its addition is completely conditioned by a succesful test.

  Are you sure? yes | no

Dave's Dev Lab wrote 02/06/2018 at 18:45 • point

Fantastic presentation at FOSDEM!

  Are you sure? yes | no

Modzer0 wrote 01/31/2018 at 21:54 • point

You are aware that there are 65C02 and Z80 based processors and microcontrollers still in production?

  Are you sure? yes | no

Staf Verhaegen wrote 01/31/2018 at 22:21 • point

I was aware of the WDC parts and assumed there would also be Z80 uCs. But mine will be open source and it should be possible for people to in the future base their own MCU or even full computers chips on them.

I've written a blog post on the background for going open course:
https://chips4makers.io/blog/the-buzzword-article-part-1-open-source.html

The mass produced parts will always be cheaper so if they fulfill your needs, that's also fine.

  Are you sure? yes | no

Ed S wrote 09/15/2017 at 09:53 • point

looks really interesting!

  Are you sure? yes | no

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