Mixed RTL language open source flow

A project log for Chips4Makers Pilot: Retro-uC

Chips want to be free

staf-verhaegenStaf Verhaegen 01/06/2020 at 19:100 Comments

It's been a long time I put something here and my promise for this year is to be more active. I have been working quietly on the Chips4Makers low-volume manufacturer flow.

My most recent success is to have replaced the proprietary Verific plugin for Yosys to do synthesis on VHDL code with the open source ghdlsynth-beta from Tristan Gingold.

More details can be found in my blog post.