1Make sure you have GNU make and binutils installed.
I'm using GNU Make 4.0, but I don't think I'm using any 4.0-specific features. You can probably get by with an older version if that's all that's available to you. I know that 3.81 should absolutely work.
I only use Make; however, if you need to install the RISC-V GCC from sources, you'll also need the binutils. GCC's installation instructions should help you if you need them.
2On your FPGA workstation, install RISC-V compatible, 64-bit version of GCC and binutils.
I'm using GCC 5.6.0 personally; I believe the latest is 7.0.
3On your FPGA workstation, install Xilinx Webpack ISE 14.7.
You may also use any compatible version of Webpack ISE that works for you. I selected this version because it was the latest which supported the Spartan XC3S1200E chip on my board. (DISCLAIMER: I remember having to fight a battle with ISE to get it properly installed, due to a missing library. Alas, I no longer remember details.)
4Install Digilent's programming software.
For Linux, you're looking for a tool called "djtgcfg". Digilent keeps re-organizing their website on me, so I don't remember where I got it from last time, and Google doesn't report any current results. However, if you poke around on the forum, you can probably find where to download it. I wish I had better information than this. :(
5Install the Fossil SCM software.
You'll want to use at least version 2.0, so I'd recommend just going directly to http://fossil-scm.org and downloading a version for your operating system of choice there. It's a single executable file and works across Linux, MacOS, and Windows.
6Clone the Kestrel-2DX repository.
For example, on Linux:
mkdir -p /tmp/fossils cd /tmp/fossils fossil clone http://chiselapp.com/user/kc5tja/repository/kestrel-2dx kestrel-2dx.fossil mkdir -p /tmp/kestrel-2dx/trunk cd /tmp/kestrel-2dx/trunk fossil open /tmp/fossils/kestrel-2dx.fossil
7Customize the Makefile
You'll need to point the Makefile to where you installed your RISC-V version of GCC. Specifically, you'll want to edit the CC_PREFIX variable.
8Build the bootstrap ROM image.
9In ISE, create a new project. Add all the RTL to this project.
You should add all the Verilog files in the rtl/ subdirectory, and all subdirectories therein. After adding all these files, you should end up with NEXYS2 as the top-level module. If it's not, make it so in ISE.
10Build the bitstream.
With NEXYS2 highlighted (and the top-level module), you should be able to double-click on the "Generate Program File" option on the left-hand pane of ISE's window. This will kick off a (roughly 7 minute) long synthesis and PNR process that should culminate in a successfully generated bitstream file. NOTE: there will be a lot of warnings. They're safe to ignore.
NOTE ALSO: I would strongly recommend you configure your project to use JTAG Clock. You can do this in ISE by clicking on Process menu, then Process Properties..., then Startup Options, then select JTAG Clock on the drop-down labelled FPGA Start-up Clock. Click OK, then reset the jumper on the Nexys-2 board to select the same. On my board, there is a jumper just above the yellow LED which reads JTAG or ROM. Set the jumper to JTAG. This allows you to program the FPGA configuration RAM directly, without having to put wear and tear on your programming flash. You can revert your settings so as to program the flash only once you're confident everything works.