A significant reduction of the register set's size is required so I/O must be managed differently, not through the register set (instruction or RAM-mapped, to be determined). The register map is expected to be:
- D1 <= for NOP
- PC <= for INV
I shrunk the instruction word down to 16 bits. It is still reminiscent of the YGREC16 older brother but I had to make clear cuts... The YGREC8 is a 1R1W machine (like x86) instead of the RISCy YGREC16, to remove one field.
I have swapped the condition field and the ALU code field, which is now a more classical opcode.
There are two instruction forms : either an IMM8 field, or a source & condition field, followed by the src/dest field and a small opcode. The source field can also become a short immediate field (3 bits only but essential for conditional short jumps or increments/decrements).
The opcode field has 4 bits and the following values:
Logic group :
- OR => Reg OR Reg does not change Reg
- ROL (might be removed)
- ROR (might get axed too)
- OUT (yes, the system is so small that a specific I/O channel system is required, unlike #YGREC16 - YG's 16bits Relay Electric Computer that uses register-mapped I/O)
- MOV (maps to INV)
The COND field has 4 bits, more than YGREC16, so we can add more direct binary input signals. CALL is moved to the opcodes so one more code is available. All conditions can be negated so we have :
- Z (Zero, all bits cleared)
- C (Carry)
- S (Sign, MSB)
- B0, B1, B2, B3 (input signals)
Instruction code 0000h should map to NOP, and the NEVER condition.
Instruction code FFFFh should map to INV, which traps or reboots the CPU : condition is implicitly ALWAYS because it's a IMM8 format : MOV FFh PC (thus rebooting/alerting with some code placed there, if any, otherwise keep instruction at FFh equal to INV to make an endless loop)
Overall, it's still orthogonal and very simple to decode, despite the added complexity of dealing with 1R1W code.
1. Honey, I forgot the MOV