A significant reduction of the register set's size is required so I/O must be managed differently, through specific instructions. The register map is expected to be:
- D1 <= for NOP
- PC <= for INV
I shrunk the instruction word down to 16 bits. It is still reminiscent of the YGREC16 older brother but I had to make clear cuts... The YGREC8 is a 1R1W machine (like x86) instead of the RISCy YGREC16, to remove one field. Speed should be great, with a very short crritical datapath, and all instruction execute in one clock cycle (except the LDCx instructions and computed writes to PC).
I have swapped the condition field and the ALU code field, which is now a more classical opcode.
20171116: The latest evolution of the instruction format has added a 9-bits immediate field address for the I/O instructions.
20180112: Imm9 is now removed again...
20181024: changed the names of some fields
20181101: modified the conditions to change Imm3 into Imm4
There are two classical instruction forms : either an IMM8 field, or a source & condition field, combined with the destination field and a small opcode. The source field can also become a short immediate field (4 bits only but essential for conditional short jumps or increments/decrements).
The opcode field has 4 bits and the following values:
Logic group :
Beware : There is no point to ADD 0, so ADD with short immediate (Imm4) will skip the value 0 and the range is now from -8 to -1 and +1 to +8. (see 17. Basic assembly programming idioms)
Shift group (optional)
- IN / OUT (yes, the system is so small that a specific I/O channel system is required, unlike #YGREC16 - YG's 16bits Relay Electric Computer that uses register-mapped I/O)
- CALL (maps to OVL and INV)
The COND field has 3 bits (for Imm4) or 4 bits, more than YGREC16, so we can add more direct binary input signals. CALL is moved to the opcodes so one more code is available. All conditions can be negated so we have :
- Z (Zero, all bits cleared)
- C (Carry)
- S (Sign, MSB)
- B0, B1, B2, B3 (input signals, for register-register form)
Instruction code 0000h should map to NOP, and the NEVER condition, hence ALWAYS is coded as 1.
Instruction code FFFFh should map to INV, which traps or reboots the CPU (through the overlay mechanism): condition is implicitly ALWAYS because it's a IMM8 format : CALL PC FFh (thus rebooting/alerting with some code placed there, if any, otherwise keep instruction at FFh equal to INV to make an endless loop)
Overall, it's still orthogonal and very simple to decode, despite the added complexity of dealing with 1R1W code.
1. Honey, I forgot the MOV
2. Small progress
3. Breakpoints !
4. The YGREC debug system
5. YGREC in VHDL, ALU redesign
6. ALU in VHDL, day 2
7. Programming the YGREC8
8. And a shifter, and a register set...
9. I/O registers
11. Structure update
12. Instruction cycle counter
13. First synthesis
14. Coloration syntaxique pour Nano
15. Assembly language and syntax
16. Inspect and control the core
17. Basic assembly programming idioms
18. Constant tables in program space
19. Trap/Interrupt vector table
20. Automated upload of overlays into program memory
21. Making room for another instruction
22. Opcode map
23. Sequencing the core
24. Synchronous Serial Debugging
25. MUX trees
26. Flags, PC and IO ports
27. Binary translation (updated)
28. Even better register set
29. A better relay-based MUX64
30. Register set again
31. Rename that opcode !
32. Register set again again
33. Yet Another Fork
34. What can it run ?
35. More register set layout
36. More VHDL and more gates
37. R7 P&R
38. Program Counter and other considerations
39. Bus names (SRC-SRI, DST/SND)
40. Now faster without the "PC-swap" MUX
41. A diode-less balanced...