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YGREC8

A byte-wide stripped-down version of the YGREC16 architecture

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YGREC can stand for many things, such as "YG's Relay Electric Computer", "Yann's Germanium and Relay Equipped Computers" or "YG's Ridiculous Electronic Contraption". You decide !

#YGREC16 is getting pretty large and moving away from the original #AMBAP inspiration, making it less likely to be implemented within my lifetime. So here is a "back to minimalism" version with
* 256 bytes of Data RAM (plus parity ?)
* 8 registers, 8 bits each (including PC)
* fewer relays/gates than the YGREC16
This core is so simple that I focus now on other issues, such as the debug/test access port, the register set's structure, I/O, power reduction...
Like the others, it's suitable for implementation with relays, transistors, SSI TTL, FPGA, ASIC, you name it (as long it uses boolean logic)!

I give up on the idea of playing the Game of Life (the forte of #YGREC-РЭС15-bis) but I design a VHDL version because @llo sees the YGREC8 as a perfect replacement for PICs for his #SteamBot Willie !

A significant reduction of the register set's size is required so I/O must be managed differently, through specific instructions. The register map is expected to be:

  • D1  <= for NOP
  • A1
  • D2
  • A2
  • R1
  • R2
  • R3
  • PC  <= for INV

I shrunk the instruction word down to 16 bits. It is still reminiscent of the YGREC16 older brother but I had to make clear cuts... The YGREC8 is a 1R1W machine (like x86) instead of the RISCy YGREC16, to remove one field. Speed should be great, with a pretty short critical datapath, and all the instructions execute in one clock cycle (except the LDCx instructions and computed writes to PC).

The fields have evolved with time (I have tried various locations and sizes). For example:

20171116: The latest evolution of the instruction format has added a 9-bits immediate field address for the I/O instructions.
20180112: Imm9 is now removed again...
20181024: changed the names of some fields
20181101: modified the conditions to change Imm3 into Imm4
20180112: Imm9 back again !

There are 18 useful opcodes (plus INV, HLT and NOP), and most share two instruction forms : either an IMM8 field, or a source & condition field. The source field can be a register or a short immediate field (4 bits only but essential for conditional short jumps or increments/decrements).

The main opcode field has 4 bits and the following values:

Logic group :

  • AND
  • OR
  • XOR
  • ANDN

Arithmetic group:

  • CMPU
  • CMPS
  • SUB
  • ADD

Beware : There is no point to ADD 0, so ADD with short immediate (Imm4) will skip the value 0 and the range is now from -8 to -1 and +1 to +8. (see 17. Basic assembly programming idioms)

Shift group (optional)

  • SH/SA direction is sign of shift, I/R(bit9) is Logic/Arithmetic flag.
  • RO/RC direction is sign of shift, I/R(bit 9) allows carry to be rotated.

Control group:

The COND field has 3 bits (for Imm4) or 4 bits, more than YGREC16, so we can add more direct binary input signals. CALL is moved to the opcodes so one more code is available. All conditions can be negated so we have :

  • Always
  • Z (Zero, all bits cleared)
  • C (Carry)
  • S (Sign, MSB)
  • B0, B1, B2, B3 (input signals, for register-register form)

Instruction code 0000h should map to NOP, and the NEVER condition, hence ALWAYS is coded as 1.

Instruction code FFFFh should map to INV, which traps or reboots the CPU (through the overlay mechanism): condition is implicitly ALWAYS because it's a IMM8 format.

Overall, it's still orthogonal and very simple to decode, despite the added complexity of dealing with 1R1W code.


Logs:
1. Honey, I forgot the MOV
2. Small progress
3. Breakpoints !
4. The YGREC debug system
5. YGREC in VHDL, ALU redesign
6. ALU in VHDL, day 2
7. Programming the YGREC8
8. And a shifter, and a register set...
9. I/O registers
10. Timer(s)
11. Structure update
12. Instruction cycle counter
13. First synthesis
14. Coloration syntaxique pour Nano
15. Assembly language and syntax
16. Inspect and control the core
17. Basic assembly programming idioms
18. Constant tables in program space
19. Trap/Interrupt vector table
20. Automated upload of overlays into program memory
21. Making room for another instruction...

Read more »

YGREC8_VHDL.20190422.3.tgz

R7 decoder in A3P tiles

x-compressed-tar - 174.65 kB - 04/22/2019 at 01:39

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YGREC8_VHDL.20190422.tgz

a better decoder for the register set

x-compressed-tar - 173.01 kB - 04/21/2019 at 17:58

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YGREC8_VHDL.20190421.tgz

Redesigning the register set

x-compressed-tar - 155.92 kB - 04/21/2019 at 00:13

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YGREC8_VHDL.20190412.tgz

New gates library, better ALU and decoder

x-compressed-tar - 152.59 kB - 04/11/2019 at 23:23

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YGREC8_VHDL.20190404.tgz

more versions of the ALU8 decoder

x-compressed-tar - 148.85 kB - 04/04/2019 at 23:10

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View all 31 files

  • Project organisation

    Yann Guidon / YGDES09/10/2019 at 23:24 0 comments

    People are (rightfully) confused with this project, and I understand why: it's ambitious and covers many aspects at once.

    For other projects, I have split the whole project into several sub-projects, for example into an architecture ( #YASEP Yet Another Small Embedded Processor) and various implementations ( #microYasep, #Discrete YASEP...). Even for the precursor ( #YGREC16 - YG's 16bits Relay Electric Computer/ #YGREC-РЭС15-bis) I created several sub-projects ( #YGREC-Si , #YGRECmos, #YGREC-ECL... ) that clearly separate the architecture from the various technologies I wanted to explore.

    But designing a new microprocessor is more than defining an ISA and making the prototype work: it's a complex ecosystem that must be carefully crafted and every piece of the puzzle must fit right into place. I think that the following sketch give a taste of the ambition of the project :

    In fact it's not so much different from the YASEP and F-CPU, except that I can go deep in the design of everything, thanks to the simplicity of the core.

    The immediate use of Y8 would be as a softcore in FPGA projects where a tiny but easy-to-use and expandable microcontroller is required. However getting there also paves the way to more sophisticated cores and technologies...

    I admit that at this moment, I focus mostly on the ASIC and relay implementations, which hold the whole project back and I need to progress on other fronts. However some tools (such as the #VHDL library of ProASIC3 gates) are in development and should be short-term only, but are very important for the rewrite of the core in VHDL.

    Stay tuned...

  • Need help with RES60 / РЭС60 relays

    Yann Guidon / YGDES09/04/2019 at 23:35 17 comments

    At the start of 2019, I found a very interesting item on @qro_team 's eBay store : a single box of 40 low-voltage РЭС60 relays. I wish there were more !

    It's the real deal : it's DPDT (unlike the РЭС15 which is only SPDT), it's very small (great for density) and the version I have can turn on at around 2.5V at half the current of the РЭС15.

    The DPDT part is very important for several circuits, for example the incrementer for PC and the ALU. But today I focus on other less visible parts : the bit sense circuits for the memory arrays. The DRAM uses capacitors that will discharge in the coil and the lower current increases the reliability of the whole system (less sensitive to current leaks in the capacitors). The instruction PROM (on which I work at the moment) also benefits from a lower current because each line drives 16 bits and the aggregate current is then handled by a single relay... So if a current of 10mA is enough to trip one line sensor, the worst case scenario for the main driver is 160mA, which is within the tolerance of the РЭС15. It remains to be seen how long it remains reliable but this is another debate. I could make the "single point of failure" easy to replace.

    The РЭС60 I have are sold as "6 to 8V" with a coil that measures about 66 ohms. It's a -02 type (?) and all the others I find on eBay have a much higher voltage : 18V, 23V, 27V, 34V... They would certainly have a lower driving current but the voltage swing is not practical. I could try my luck if there are "12V" versions but I need another box because the 40 pieces I have at the moment is barely enough for the various circuits that require it... Who could help me ? @Artem Kashkanov  ? @[skaarj] ? ...


    According to this datasheet (and many others found online),

    there must be a marking error on my box because the -02 is rated at 270 ohms and I measured coils in the 65 ohms range... but apparently I need a 12V version, with -02 or -08 type (I still can't get the difference).

    I might have found -04 (lower voltage) that would be useful in the ALU so my -03 would be used as sensors, probably using pre-biasing, unless there is some magic reed relay that could save the circuit ? (Artem ? ;-) )


    Correction : the box is marked "00.02" so according to the references I have found, it should be a 23-34V version. Measurements disagree... I don't know what happened or if the parts were repackaged but anyway, I have them :-D

  • A Diode (P)ROM was (almost) built in a day

    Yann Guidon / YGDES09/03/2019 at 12:35 0 comments

    So I tried to build a prototype and it was almost finished in a day :-)

    32 instructions, 64 DIP-switches with 16 pins each, that's already 1024 soldering joints.

    Then 512 diodes (LL4148), linked in 8 rows, make another kilojoints :

    but it's not as hard as it sounds.

    What is still missing is the 64 column wires and the connectors. I'll also add one LED per line.

    Of course a dedicated PCB would ease assembly but this

    1. would be very costly
    2. I have more important other expenses
    3. I already have these parts in stock
    4. I don't want to waste money with a flawed PCB design that a prototype could solve.

    Anyway with 32 instructions I'll have enough room to test interesting things and it's not as hard as it looks.

    I want to make the board design modular, each board can be relocated physically on a backplane to change the address. There are 2 decoders, large MUXes for the lines and columns, that will not need changes, while the data boards can be of any type (DIP switches, solder joints or anything else I come up with).

  • Diode (P)ROM wasn't built in a day

    Yann Guidon / YGDES08/27/2019 at 21:52 0 comments

    As I build the instruction assembler and disassember, I must also provide a way to store instructions. This was already covered in #YGREC16 - YG's 16bits Relay Electric Computer in the log PROM boards.

    Things have evolved since 2017 and I now have a whole bunch of DIP switches (Log: I hope that's enough this time) and pretty large proto boards... I have just what is required to build boards with 16×4=64 instructions :-)

    But let's look at how these boards must be organised. The YGREC8 has 16-bits instructions so a higher density than the 24 bits of the YGREC16. And there are only 256 addressable instructions. That's 256×2=512 DIP switches, I have more than 700 in stock these days :-)

    Then the topology must be optimised to reduce the number of relays : how many lines and columns ?

    • 1 column and 256 lines : 1 huge MUX256, or 255 relays. HUGE...
    • 2 columns and 128 lines : 1 huge MUX128 and 16 relays to select the column, or 143 relays. Better but still not optimal.
    • 4 comumns and 64 lines : 1 large MUX64 and 16×MUX4, or 63+(16×3) = 111 relays. Good.
    • 8 columns and 32 lines : 1 MUX32 and 16×MUX8 = 31 + 16×7 = 143 : the column MUX gets too large now.

    So be it : the PROM cards are organised with 4 columns.

    I'll try to build a 8×4 board to get started... because I also need to build the 2 big MUXes for lines and colums. Where are my boxes of SMD diodes ? :-D

  • More assembler panel stuff

    Yann Guidon / YGDES08/25/2019 at 13:09 12 comments

    I have received and tested all the interlocked switches :-)

    and I'm updating the layout and dimensions, using the diagrams I have found on the web:

    So far the layout of the panel is:

    but many questions are still in the air...

    I can print with my laser printer to the exact scale so this will be very useful: no need of a CNC ! but it only moves the problem around.

    How can I transfer the toner to the front panel (aluminium) for the labels of the buttons ?

    I added the "SEL" button : it's a SPDT switch that selects which circuit gets the power/signal, either the assembler panel or the program ROM. That makes now 3 switches (IMM8, NEG and SEL) and I haven't decided/found which model to use. I need a low-force, high-endurance switch with a long lever (10mm or 12mm ?) so the drill diameter is undetermined (until I find THE model that fits).

    The SEL button changes several things, because initially I wanted to use a 16-pole dual throw switch to select the value sent to the instruction decoder. The operating force and endurance would not be satisfying because I want to alternate between both sources easily and fast. Now the instruction bus is shared between the ASM panel, the instruction ROM and the eventual electronic/remote interface.

    For the YGREC16 with 24 instruction bits, I started with positive logic, then realised it would be more complex for the driving electronics so I changed to a different driving system where PNP transistors just pull the signal to 0V. But overall this is not easy to manage and a return to "positive logic" seems unavoidable.

    Another consequence is that the outputs of the asm panel must be "diode protected" because some signals can be shorted by the switches. This is not a problem when the panel is operated alone but it will interfere in some cases with the ROM and the external interface. Another version of the diagram is necessary... So here it is!

    There are now 38 diodes now. It is not a tragic increase but there is a good side effect : all the signal paths have one diode drop, everything is now balanced !


  • The disassembler panel

    Yann Guidon / YGDES08/08/2019 at 02:31 0 comments

    As you can see at Log: Don't go full Numitron ! Unless... OK whatever.,  I started to design the disassembler and I totally renewed the look:

    This version now shares a pair of Numitrons to display either the SRI or the Immediate field, which saves a bit of room and 2 tubes but adds some complexity in the decoding logic (yet not enough to scare me, of course). The above display is not compliant with the normal assembler but close enough and it gets the job done :-)

    I draw a lot experience from the #Numitron Hexadecimal display module so I know what to expect and what to do to display the desired patterns on the 7 segments. There is no technical challenge anymore to display the CND, SND, SRI and Opcode fields, but it's still a lot of work, in particular for the Opcodes: this decoder not only must display 19 words on 3 tubes, but also sends control signals to enable the other fields.

    It's going to be small and gorgeous but behind the front panel, the electronics will be pretty dense and draw a significant amount of power...


    Damnit I forgot that IN/OUT have 9 bits of immediate address...

    The Imm field will create more problems, on top of the multiplexing with the SRI decoder. The field must select the width between 4, 8 and 9 bits. The last case is not a problem because an address is just a positive number. Imm4 is sign-extended to 8 bits (easy: 4 relays) but should Imm8 be represented as a signed number ?

    Then there is the special case of Add imm4(>=0) where Imm4 is incremented.

    The easy way is to simply display the number as is, and forget about it, though the display would not be accurate. It would even be misleading.

    But then, if the Add correction or the negative display are implemented, an increment unit is required. And negative numbers require a XOR to transpose to positive numbers. This means more circuits in front of the display modules...

    But with negative numbers, the added Numitron can have another segment used, for the sign bit:

    To keep the system modular (and help with development, debug and repairs), I think I'll make 3 modules with 3 Numitrons each, with identical connectors. I can then develop all 3 groups in parallel.

    The connector is probably IDC 2×13 : each Numitron has 7 segments + 1 common signal, or 8 wires, and 3 Numitrons need 3×8=24 wires. Add two positions for a pair of pins for the optional red Glühbirnchen and we have exactly 26 pins.

  • Updated wiring of the new assembler panel

    Yann Guidon / YGDES08/04/2019 at 16:41 0 comments

    I nailed it !

    I solved a "bug" and I now use "normal" hexadecimal encoding knobs. This required a big redesign... There are now 29 diodes but only one per signal so I can use old, low-current point-contact D9K.

    Another big difference is a rotary 4-poles 3-throw selector ! It selects between the Imm8, Imm4 and Register forms. I could use interlocked switches as well but their mechanical installation might be more complex, more holes and alignment...

    I'm only missing one row of 8 switches for now, but I can start the construction :-)

  • ASM panel dimensions

    Yann Guidon / YGDES07/31/2019 at 00:40 2 comments

    As I received the buttons, I was able to not only get electrical information but also dimensions. I updated the layout:

    The 50 buttons easily fit in a 18×18cm square so 20×20cm is a safe dimension for this panel.

    Remember that it's only the instruction, and more things are done in other panels :

    • The disassembly panel shows the instruction being sent to the core (it's the reverse of the ASM panel)
    • The control panel selects the source of the instruction, generates the clock, sends the clock pulses to the  core (one-shot, several ones or continuously)
    • The debug panel has several event counters that can stop the core...
    • More panels display the inner state of the core

  • Interlocked switches galore !

    Yann Guidon / YGDES07/29/2019 at 01:44 1 comment

    I received quite a few switches and more will come later !

    These are 10 interlocked switches, with their caps, and they are just like I wanted :-)

    2 of them will be used for the opcode selector.

    For the other selectors I needed somethign more simple and pre-made, and I have found it in the form of the 8-channels video selectors. And I have a good surprise ! Look:

    I expected the box to contain a single PCB but there are two, making the switches assembly very easy to remove !

    2 screws and 2 connectors to remove, and there you have the module :-)

    The traces are easy to follow and they are already conveniently wired for my purpose :

    The SRI, SND and CND fields are 3 bits wide, and the selector outputs 3 bits, which is a great match.

    I can wire the switches' inputs to a common rail, such that the 3 output bits will contain the binary code of the selected button. I can also bind the boards together to make a more sturdy structure (I have 2 but need a 3rd for the conditions).

    There is a last technical problem though, with the hexadecimal encoder : the lower nibble requires a type of switch I don't own... But @Artem Kashkanov has the perfect part ! From Russia, of course ;-)

    This selector has individual SPDT switches for each bit, making my diodes hack possible :-)

    I'm still missing a few extra switches but they'll come soon enough.

    At least I successfully designed a fully-passive assembler panel, with only one diode drop on certain signals, and no requirement of external power (no relay or other logic). The panel can work with relay logic, transistors, TTL...

    Time to think about the disassembler panel now ;-)


    I have easily modified 2 8-ways selectors !

    I can say it works very nicely :-)

    I'm waiting for the delivery of the 3rd module so I can have all the necessary buttons for the SND, SRI and CND fields.

  • More wiring of the new assembler panel

    Yann Guidon / YGDES07/23/2019 at 02:32 0 comments

    I figured a few things...

    Here is the aggregated schematic for the opcode field :

    It might look complex but most of the complexity has been examined in the previous log and it's basically a pair of binary encoders that have been chained through the XT button.

    The tricky part is the simultaneous selection of buttons from both rows : some combinations would disrupt the binary code. This occurs when the "lower row" (AND through CALL) has one button pushed with a code that has more than one set bit (ADD, SUB, CMPS, ANDN). There is a potential path that is now broken by 10 diodes. And since the locked switches work together, only one switch is now required.

    The "upper row" OTOH doesn't need diodes because the switches are interlocked. There is no place where different signals are brought together, except when a switch is pushed.

    I'm working on the other switches...


    More schematicsing :-D


    Going further, I added the dual hex encoders and tried to join everything together:

    It's almost complete. b2,b1,b0 didn't change, nor did b15,b14,b13,b12,b11. The SRI field (and the LSB of the condition) can be combined with the lower half of the immediate field, while the condition field (plus a couple more bits) can be combined with the higher half.

    However the simultaneous activation of the lower half for both Imm4 and Imm8 is more complicated and not yet implemented. The trivial version would use another diode, so the total drop would be 3 diodes !

    I need a method to reduce this drop, I suspect there is a way to keep it down to 1 drop but I need to test it...

    And I should switch from dia to EAGLE :-D


    I solved a potential problem caused by several diode drops in series :

    The free switches for the XT button isolate the main signals and prevent the use of diodes. The hexadecimal encoder requires separate switches, so each signal can be driven by a pair of diodes (instead of one diode at the output).

    There is one remaining switch and I wonder how to use it to remove more diodes...

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castvee8 wrote 04/13/2019 at 22:57 point

I so love your commitment and enthusiasm ! I was playing with vacuum tube calculators a bit since last year an just keep going down the rabbit hole. Your projects seem to at least make purposeful sense.

  Are you sure? yes | no

Yann Guidon / YGDES wrote 04/14/2019 at 08:56 point

That "purposeful sense" may look drowned into the proliferation of projects, angles and ideas but it is still clear to me since it's my main hobby since 1998 at least :-D

I'm glad you enjoy !

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Yann Guidon / YGDES wrote 11/04/2018 at 07:11 point

Another note for later :
writing to A1 or A2 starts a fetch from RAM. In theory the latency is the same as instruction memory and one wait state would be introduced. However the processor can also write directly so the wait state would be only on read to the paired data register...

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Yann Guidon / YGDES wrote 11/04/2018 at 06:55 point

Note for later : don't forget the transparent latch on the destination register address field, for the (rare) case of LDCx, because the 2nd cycle doesn't preserve the opcode etc.

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Yann Guidon / YGDES wrote 11/04/2018 at 07:18 point

OK, not a transparent latch, but a DFF and a mux, plus some logic to control it.

-- DFF, every cycle :

SND_latched <= SND_field;

LDCx_flag <= '1' when (LDCx_flag='0' and opcode=opc_LDC and writeBack_enabled='1')   else '0';

-- MUX2 :

WriteAddress <= SND_latched when LDCx_flag = '1' else SND_field;

______

Note : LDCx into PC must work without wait state because it's connected directly to SRI, as an IMM8, and no extra delay is required. PC wait state is required for ADD/ROP2/SHL and IN.

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Frank Buss wrote 10/27/2018 at 12:51 point

Do you really plan 8 byte-wide registers? This would require thousands of relays :-)

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Yann Guidon / YGDES wrote 10/27/2018 at 14:26 point

no :-)

8 registers, 8 bits each = 64 storage bits.
1 relay per bit => 64 registers


The trick is to use the hysteretic mode of the relays :-)

  Are you sure? yes | no

Frank Buss wrote 10/27/2018 at 16:17 point

Ok, makes sense. Maybe change the project description, someone might think you are planning a 64 bit architecture.
BTW, could this be parametrized for the address and data size? If you implement it in VHDL, you could use generics for this, would be no additional work to use just the generic names instead of hard coded numbers. Except maybe some work for extending the instruction opcodes.

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Yann Guidon / YGDES wrote 10/27/2018 at 17:16 point

Frank : DAMNIT you're right !

I updated the description...

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Yann Guidon / YGDES wrote 10/27/2018 at 17:19 point

For the parameterization : it doesn't make sense at this scale. Every fraction of bit counts and must be wisely allocated.

Larger architectures such at #YASEP Yet Another Small Embedded Processor  and #F-CPU  have much more headroom for this.

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Bartosz wrote 11/08/2017 at 16:40 point

this will working on epiphany or oHm or other cheap machine?

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Yann Guidon / YGDES wrote 11/08/2017 at 18:07 point

I'm preparing a version that would hopefully use less than half of a A3P060 FPGA, which is already the smallest of that family that can reasonably implement a microcontroller.

But it's a lot less fun than making one with hundreds of SPDT relays !

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Bartosz wrote 11/14/2017 at 14:13 point

Question is price and posibility to buy

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Yann Guidon / YGDES wrote 11/14/2017 at 16:08 point

@Bartosz : what do you want to buy ?

If you can simulate and/or synthesise VHDL, the source code is being developed and available for free, though I can't support all FPGA vendors.

If you want a ready-made FPGA board, that could be made too.

If you want relays, it's a bit more tricky ;-)

I have just enough RES15 to make my project and it might take a long while to succeed. There will be many PCB and other stuff.

However if, in the end, I see strong interest from potential buyers, I might make a cost-reduced version with easily-found minirelays. I don't remember well but the Chinese models I found cost around 1/2$ a piece. Factor in PCB and other costs and you get a very rough price estimate... It's not cheap, it's not power efficient, it's slow and won't compute useful stuff... But it certainly can make a crazy nice interactive display, when coupled with flip dots :-D

So the answer is : "it depends" :-D

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