Bus names (SRC-SRI, DST/SND)

A project log for YGREC8

A byte-wide stripped-down version of the YGREC16 architecture

Yann Guidon / YGDESYann Guidon / YGDES 10/23/2018 at 22:300 Comments

Today I try to make the bus names more coherent and bring them closer to the YASEP conventions.

The Y8 has 2 register address fields where one can also be an immediate value and the other becomes the destination. The names can be a bit confusing and the early YASEP had something like SRC1 and SRC2, which didn't really help because each bus could only do certain operations.


This is the bus that brings a Source register, can perform Negation (this is where the XOR applies) and can become a Destination. For the ROP2 operations, this is the operand that gets negated (complemented) in ANDN and for SUB, this is the register that gets subtracted from the other operand.


This Source operand can be either be a Register or an Immediate value (signed 4 or 8 bits). This field gives the positive value in a subtraction or comparison, and can be a literal value instead of a register number.

It will take a while until I've updated all the diagrams...

2019/4: it's updated :-)