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Census of the gates

A project log for YGREC8

A byte-wide stripped-down version of the YGREC16 architecture

Yann Guidon / YGDESYann Guidon / YGDES 04/21/2019 at 20:050 Comments

It's time for a little census.

[yg@Host-002 VHDL]$ grep -r 'entity' * |grep 'port' |grep 'map' |sed 's/.*entity //'|sed 's/ port.*//'|sort|uniq 
AND2  
AND2A
AND3
AND3A 
AO1
AX1C  
CLA3
INV   
MX2
NAND2 
NAND3 
NAND3A
NOR2  
NOR3  
NOR3A 
OA1A
OR3 
XA1
XO1
XOR2  

 (I removed the complex unit names by hand)

There are 20 gates so far, more, and more complex, than what #Shared Silicon provides (only INV, NOR, NOR3, NAND2, NAND3 and some T-gates).

I believe that by using more complex gates with more inputs (but reasonably so), there is a bit of performance and size benefit. I don't see any roadblock to get the missing gates : either I can make mine easily, or I borrow from existing free libraries.

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