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INC8 ASICified

A project log for YGREC8

A byte-wide stripped-down version of the YGREC16 architecture

Yann Guidon / YGDESYann Guidon / YGDES 07/15/2020 at 04:400 Comments

After spending some quality time in the ASIC world for 107. Choosing the gates, it was time to practice a bit. The target of choice is of course the INC8 unit, which has been significantly modified after a little session with circuitjs :

The circuit starts with buffers so ensure that the fan-in is 1 for all the bits. And since simple buffers invert, the rest of the circuit uses a negative logic and the AND trees are replaced with ORs.

The fanout needs to be "micromanaged" unlike with FPGAs. "Normal" gates are supposed to have a fanout of 1 and some buffers provide x2 and x4 strength, but they invert again...

Apart from the ORs directly tied to the final XORs (which can be combined into AX1D ) we find 2×NOR3, 2×OR3 and 1×OR2. The fanout buffer is merged into the final inverter of the ORs, except where a large fanout (6) is needed : there, the NOR2 has a strength of 2 to drive two buffers with strength 4. The "combined" variant with OR is kept in some places to keep the diagram & code compact.

For the AX1D ( Y=(A or B) xor C, also named xoon21 in the some libraries) the OR is easily merged as a NOR instead of INV of one of the inputs.

Overall, the circuit has grown in complexity, or in fact : better details. There is no use of the new fancy 4-input gates but the AX1D is very welcome... We'll see how the ALU is influenced later !   


So I added some extra features to test the circuit easily :-) see  INC8_ASIC_test.cjs

The VHDL version was easy to adapt. The first results are nice though are not very nuanced :

 Latency of the 9 outputs :
      Output#0 : 2
      Output#1 : 3
      Output#2 : 3
      Output#3 : 5
      Output#4 : 5
      Output#5 : 5
      Output#6 : 5
      Output#7 : 5
      Output#8 : 5
  
  Fanout:  Count:  .........|........
      1 :     17 - *****************                                 
      2 :      6 - ******                                            
      3 :      5 - *****                                             
      4 :      2 - **                                                
  
   Depth:  Gates:  .........|.......
      0 :      8 - ********                                          
      1 :      8 - ********                                          
      2 :      5 - *****                                             
      3 :      3 - ***                                               
      4 :      6 - ******                  

 The latency is OK and balanced. Most MSB depend on the result of a high-fanout signal, which has been broken into 2 parallel sub-signals. In the grand ASIC scheme of things, that amounts to about 2 gates delays (easily) so it's not inaccurate. Anyway this helps synchronise most MSB as their results arrive at about the same time, with a critical datapath that has been spread/smeared across the circuit.

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