Breakpoints !

A project log for YGREC8

A byte-wide stripped-down version of the YGREC16 architecture

Yann Guidon / YGDESYann Guidon / YGDES 11/05/2017 at 17:530 Comments

Reading ... and a familiar thought resurfaced !

I forgot the breakpoint(s).

At least one trap on a given instruction address would be nice, right ?

This happened before with the #Discrete YASEP  at 6. Dear SN74HC688  and other handy traps would be triggered on writing to a given register or on detection of a given value on the result bus. These trap signals would really help, not just with debugging the software, but also the hardware !

Another thought : add a cycle counter. However the electromechanical panel versions I have found are limited to 8 to 10 pulses per second only, while I expect more than twice that speed...

Examples found on eBay:

Maybe a predivider would help but... the missing least significant digit would be more than welcome.

Another eBay image from

And this one is limited to 10 I/S as well :

So I doubt the claim that this chinese model works at 60Hz The line "Input Power : DC 24V 50/60Hz" makes me believe it's an editing error.

But mostly, these counters don't provide an output signal when a given count is reached so their usefulness is "only informative". A nice decorative gadget.

Anyway, the bitwise comparison of two numbers is pretty easy with relays. First, wire the relays in series to make a large AND gate. Then complement the relays with other relays to make XORs. This amounts to 2 relays per bit. There is also a version of XOR with 1 relay per bit but it relies on both operands to use rail-to-rail signals (not just on/off).

For ease of design and economy, the values to compare could be entered in binary with individual SPDT switches. But you know, binary is SOOOOO 50s. Hexadecimal knobs please !

Unfortunately, my knobs are SPST. This means that one relay per bit is still required to transform the on/off signal into rail-to-rail signals. So we're back to 2 relays per bit. Convenience has won again...