The YGREC family is pretty straight-forward. The main sequential elements of the core are the register set and the flags so the whole rest is combinatorial and the control signals directly map to the instruction word. So we can control the core simply by playing with the instruction word, even when not executing any program.
This leads to a similarly very simple debug system that hijacks the instruction memory system, thus cutting the whole processor in half and adds an optional slice in the middle, as shown in this new diagram :
The beauty is that it's totally modular, so far I have focused on the assembler and disassembler but other modules include the control of the instruction address, the comparators that make up the breakpoints sub-system, and the sequencer to start/step/stop the datapath.
A finished YGREC can work without the debug modules, or any number of them. In a FPGA or ASIC, this system is also easy to implement and it provides a single point of control that can be read and written using a scan chain/shift register, using SPI or JTAG.
The minimal internal state and the debugging information are:
- Current instruction address (can be selected as the core's PC or a forced value)
- Current instruction word (either coming from memory or a forced value)
- the SRC and DST operands, as well as the RESULT value
- the C/S/Z flags
With all these values, as well as the ability to inject any information through the instruction bus, the whole core can be dumped and controlled.
Note that the instruction word can be controlled and give immediate results, yet the core is halted. If the result is satisfying, the user can validate it with a "step" pulse that will record the result in the register set and the flags. So the instruction can change at will, without any effect, even in the middle of a program: this can help dump the contents of the registers or even memory regions. The whole state can be read and changed, before the program resumes its normal execution path.
The funny side effect is that, to send "explore" the core through such a debug interface, a sequence of commands is required, which looks a lot like a "program" except without the possibility to jump or loop. Debug thus uses snippets of code that use the normal CPU assembler tool, only extended to support sequencing and debug signals. The processor is now its own debugging language !
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