ALU in VHDL, day 2

A project log for YGREC8

A byte-wide stripped-down version of the YGREC16 architecture

yann-guidon-ygdesYann Guidon / YGDES 11/10/2017 at 06:030 Comments

Against all odds, the first attempt at a VHDL ALU worked the very first time. I have not found any error in the logic and adder code, can you believe it ?

I must admit that the experiences with the YASEP and its long evolution made writing this ALU a breeze. I was prepared for many of the usual "considerations" to take into account and I looked a bit at for some old tricks. However the Carry LookAhead logic is a first for me. In case this implementation is slower than standard/custom implementations, I'll make a version with the standard "+" operator, users will try both and keep the fastest one.

There are some changes today : there are two result outputs, one for the ROP2 and the other for the ADD. This is because they have wildly differing latencies and the rest of the core must do the proper MUXing. This will depend on other parameters that are outside of the ALU. The Z and S flags are outside, as well.

There is another "idiosynchrasy" : the borrow bit is inverted from the carry bit, to save a XOR in the Critical DataPath. This is a bit confusing at first... Like the Z flag that is 0 when the result is zero (because it's just a big OR). The Sign flag however is just a copy of the MSB, nothing weird there :-P

Anyway : Carry occurs when Cout=1, but borrow occurs when Cout=0. And the Cin must be set for SUB/CMP to work.