Structure update

A project log for YGREC8

A byte-wide stripped-down version of the YGREC16 architecture

Yann Guidon / YGDESYann Guidon / YGDES 11/13/2017 at 18:590 Comments

I found that I made a few errors in my precedent diagram and I have updated several aspects. Here is only an early draft, until @llo  makes a vector version.

The condition block on the left is not well laid out but hopefully @llo  will make it better :-D

Back to VHDL now...

And I updated the instruction format diagram :

yup the condition Negation flag has moved... I don't know why. But it's coherent with the VHDL code.

20171203 : I got a stable and nice diagram of the core !