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First synthesis​

A project log for YGREC8

A byte-wide stripped-down version of the YGREC16 architecture

Yann Guidon / YGDESYann Guidon / YGDES 12/06/2017 at 03:530 Comments

Can you believe that the source code synthesised and place/routed on first try and reached an estimated 49MHz performance on A3P060 ?

The core occupies about 570 versatiles (3-input cells) which leaves 2/3 of the FPGA (1K LUT3) for GPIO and peripherals :-) [I originally expected about 700]

The source code is not used correctly (many registers are mapped to I/O pads, an artefact from the coding style) so performance can only increase and the system fits nicely in the small #ProAsic3-Stamp !

There is still a lot of work to do but it's looking great so far.

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