Inspect and control the core

A project log for YGREC8

A byte-wide stripped-down version of the YGREC16 architecture

Yann Guidon / YGDESYann Guidon / YGDES 01/01/2018 at 05:310 Comments

The YGREC8 core is a rather simple collection of sequential and logic gates, that are usually controlled by a stream of instructions coming from the instruction memory.

The core can also be controlled by an outside debugging device through a "test access port" (TAP) that provides a minimal but essential interface to access the state of all the internal resources (memories, registers, IOs...) by reading or writing a sequence of user-invisible registers.

The complexity and size of the TAP and the internal resources must be kept as small as possible to keep the design fast and compact. The TAP can be removed when debugging or inspection are not required, to save room and increase speed.

The basic features are :

The CONTROL register provides several bits:

The INSTRUCTION (INST) register does more than allow execution of arbitrary instructions, it's a way to control the state of the datapath : the DST, SRC and RESULT buses are combinatorially and directly affected by the SRC and DST fields of the instruction, and visible immediately.

More complex interactions and control comes from sequences of values written to the CONTROL  and INSTRUCTION registers, by allowing results of fake instructions to be registered or not.

More registers will be available for read/write access to provide breakpoints.

The debug system has one logic view (read and write registers) that can be implemented in any suitable way with circuits. The physical interface to the registers could be synchronous, asynchronous, parallel, multiplexed or serial... But the user can access these registers (as described above) :

The timing, as well as the order of writing and reading information, are critical. For example, reading the registers while the core is running makes no sense because data will be garbled.