At this moment I work on a more formal code for the MUX parts. In other words I'm digging again in a pet topology project. This makes the VHDL code better, because I realise I use MUX8 in various places yet I don't get the best out of them. For example, even though I built the Register Set out of balanced control trees, I didn't use this technique for the conditions. So I started writing MUX8 components in VHDL... I haven't uploaded the new code archive but when I do, look at MUX8.vhdl. I should also rewrite the REG8 module by using these enhanced MUX8.
The next step is the large MUX64 used by the serial debug system (see 24. Synchronous Serial Debugging). I'd like to design it algorithmically but I haven't cracked yet the algorithm. Is there a simple one ?
20180227 : algorithm cracking in progress. Meanwhile, I already have one topology/solution for MUX64 :
It's going to be fun to write this in VHDL...