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A project log for YGREC8

A byte-wide stripped-down version of the YGREC16 architecture

yann-guidon-ygdesYann Guidon / YGDES 01/12/2018 at 15:140 Comments

As of 20180112:

opcode
value
R/I8nameImm8condReg
SRC
flag
description
0h
OR



SZDST = SRC | DST
1h
XOR



SZDST = SRC ^ DST
2h

AND



SZDST = SRC & DST
3h
ANDN



SZDST = SRC & ~DST
4h
CMPU



CSZCoMPare, Unsigned
(SUB with no write)
5h
CMPS



CSZCoMPare, Signed
(SUB with no write,
MSB tweaked)
6h
SUB



CSZDST=SRC+ (-DST)
7h
ADD



CSZDST = SRC + DST
8h
SHR



SZSHift Right
9h
SHL



SZSHift Left
Ah
SAR



SZShift Arithmetic Right
Bh
ROL



SZROtate Left
Ch0
IN
NONO
Read INput port
Ch1
OUT
NONO
Write OUTput port
Dh0
LDCLNO

SZ?Load Constant Low
(read instr memory)
Dh1LDCHNO

SZ?Load Constant High
(read instr memory)
Eh
MOV


SZCopy register value
Fh
CALL


SZ?SRC=>PC, PC+1=>DST
FFh

OVL


SZ?Halts core, wait for
loading of OVerLay.
Special case of
CALL PC (SRC=>PC)
FFFFh1
INV
NO
SZ?INValid instruction
(halt core)
Special case of
OVL FFh

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