• testing logic... ok

    Adam Lange11/25/2017 at 20:46 0 comments

    The c function that produces the pwm 'on times' is working now.  The next step is to work on using that c code to synthesize Verilog.

  • mmmm.... nope, something is wrong

    Adam Lange11/22/2017 at 05:46 1 comment

    I'm implementing logic that takes as an input a voltage vector in space vector space, and outputs values that the pwm timers use to generate the inverter gate drive logic.  I'm using Vivado-HLS to do this.  I've written some code, C code!  Eventually Vivado-HLS will turn that code into Verilog, but the first step is to create a test that runs on-laptop to verify that the C code to be transformed actually behaves the way it should before synthesizing Verilog from C.  Here's the current output from the test:

    When this is working as it should, it will look like three sinusoids spaced with 120 degree phase angle, not like three winking skeletons.

  • Gettting a foothold on High-Level Synthesis

    Adam Lange11/21/2017 at 06:37 0 comments

    The PWM timers are working (there's working and then there's working good.... With no rigorous testing I will only venture to say working).

    The timers need to be fed with values to go into their compare registers.  The timers were pretty easy to code in Verilog.  The logic to feed the timer compare registers [1] is much more daunting.  We're talking multiplication, division, square roots (might not need to do those on-line...),  building up expressions using conditional logic.  Enter HLS.

    HLS - High-Level Synthesis can for example take C and turn it into Verilog or VHDL.  That's pretty cool if you ask me.  I'm using Xilinx's Vivado-HLS.  It will synthesize Verilog or  VHDL from C, C++, systemC, or OpenCL.  I'm not sure if I'm going to use C or C++ yet.  I think it will come down to the data types.  With C++ you get a fixed point representation that you don't get with C.  We'll see what happens here.

    I clawed at the air for a little while before I found a good getting started foothold.  First I looked at a few tutorials using Vivado-HLS including the official Vivado-HLS tutorials.  For the task at hand  they felt very slow and too detailed.

    The foothold: ug902-vivado-high-level-synthesis.pdf

    [1] If you're curious about the logic I recommend the book "Vector Control of Three-Phase AC Machines by Quang and Dittrich". 

  • Simulating PWM timers

    Adam Lange11/18/2017 at 04:37 0 comments

    I spent some time reading the docs and working tutorials for Vivado's simulation tools.  I implemented the basic pwm counter in verilog and ran in in a testbench.

  • Initializing the MegaMoto's

    Adam Lange11/18/2017 at 04:17 0 comments

    I hooked up a DC motor to the MegaMoto board and wrote some verilog to PWM one of the half bridges.

    Next I'll be working to implement space vector modulation.

  • The quadrature counter is operational

    Adam Lange11/15/2017 at 05:22 0 comments