The PWM timers are working (there's working and then there's working good.... With no rigorous testing I will only venture to say working).

The timers need to be fed with values to go into their compare registers.  The timers were pretty easy to code in Verilog.  The logic to feed the timer compare registers [1] is much more daunting.  We're talking multiplication, division, square roots (might not need to do those on-line...),  building up expressions using conditional logic.  Enter HLS.

HLS - High-Level Synthesis can for example take C and turn it into Verilog or VHDL.  That's pretty cool if you ask me.  I'm using Xilinx's Vivado-HLS.  It will synthesize Verilog or  VHDL from C, C++, systemC, or OpenCL.  I'm not sure if I'm going to use C or C++ yet.  I think it will come down to the data types.  With C++ you get a fixed point representation that you don't get with C.  We'll see what happens here.

I clawed at the air for a little while before I found a good getting started foothold.  First I looked at a few tutorials using Vivado-HLS including the official Vivado-HLS tutorials.  For the task at hand  they felt very slow and too detailed.

The foothold: ug902-vivado-high-level-synthesis.pdf

[1] If you're curious about the logic I recommend the book "Vector Control of Three-Phase AC Machines by Quang and Dittrich".