The story so far...
We can control the LED drivers to scan out a row in the 12 sections, but we haven't figured out how to ask the CPLD to switch to the next row (or why the CPLD owns row MUX).
Current "Request For Investigation": Figure out what the FPGA sends to the CPLD on the front board to get it to scan through the six display rows. If someone has a working display a logic analyzer capture of the FPGA->CPLD lines (ideally from boot) would be great.
Setting up and sending pixels to the LED row drivers, and turning on pixels (and the 3 self-test LEDs on the back)
Communications through the IN and OUT connectors.
Scanning more than the first of the multiplexed rows; the CPLD is in charge of stepping these it seems.
The panel is divided into twelve segments of 16x6. Each segment is driven by three Texas Instruments TLC5941 16-channel LED drivers. Each driver controls one color of the tri-color LEDs. The three drivers have their serial data cascaded, with the first controller in the cascade being Red, then Green, then Blue. Anode voltage is switched to each of the six rows of LEDs in sequence via a transistor controlled by the CPLD.
The 96 LEDs in the segment are controlled by only 16 driver channels by multiplexing the rows' LED anode voltage (TLC5941 switches the cathode side). Each of the 36 rows has a transistor between the panel's +4.5V input and the LED anodes. All like-numbered rows' transistors are connected to a common control pin on the CPLD. The CPLD cycles through them in sequence as instructed by the FPGA, synchronized with the incoming display data.
Take care when rewriting HDL for the FPGA. Because the LEDs are expecting to be run at only 1/6 duty cycle, they may theoretically be damaged if they are not cycled as quickly by user HDL. (For experimenting, consider using the calibration LEDs on the rear of the panel, which are not multiplexed.)
There are three I2C devices on the LED panel, an EEPROM, a temperature sensor and an ambient light sensor used for brightness calibration.
Most of the LED driver control pins are brought out to the data connector by way of two buffers. The remaining signals (SOUT for each driver string) are fed to the CPLD.
Back Panel Connectors
Input connector (TE AMP 206486-2 - mates with 206485-1)
|Pin||Function||FPGA Pin||FPGA LVDS Pair||FPGA Direction|
|1||+VIN. Connected to a Linear LTC1778. |