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A project log for RISC-V Instruction Set Architecture

RISC-V is a free, open general-purpose instruction set architecture developed at UC Berkeley, designed to be flexible and extensible.

Yunsup LeeYunsup Lee 08/21/2014 at 06:130 Comments

RISC-V at HotChips-26

The RISC-V team was out in force at the HotChips-26conference manning a sponsor booth.  Alongside a bunch of cool giveaways, including RISC-V buttons and bumper stickers, we had several demo boards at the conference. From left to right: a dual-core Rocket+Hwacha system in IBM's 45nm SOI process, running up to 1.35GHz, a single core Rocket+Hwacha system in ST 28nm FDSOI process running down to 0.45V, and an FPGA prototype running on a Xilinx Zybo board.

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