Zynq UtraScale+: HDMI in + Sobel filter +HDMI out

HDMI demonstration on the EMC2 development platform from Sundance with signal processing.

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The demonstration runs on a stand-alone EMC² Development Platform PCIe/104 OneBank™ featuring a Zynq Ultrascale+ZU3EG with Quad-core ARM Cortex-A53 and a re-configurable FPGA Logic.
The quad ARM processor cores have direct access to the DDR4 memory that provides 1GByte of storage.

The purpose of this demo is to allow real-life data, in this case a video-stream from a HDMI Output device to be loaded into the Zynq’s DDR memory, processed and then displayed again on a second HDMI-Input device (typically a monitor).
In this demonstration, a VITA57.1 FMC® compatible Daughter Card is plugged to the EMC²-DP to provide HDMI input/output capabilities. Also, a Sobel filter is implemented to process the video data coming from an HDMI camera.
This demo shows how most computing intensive tasks are implemented, where possible, in hardware, both using standard or custom IP cores and by using High Level Synthesis tools.

Hardware design

The demo is based on a customed design platform developed in Vivado 2017.2.

The resolution of the input and output video data is set at 1280x720 with a 65MHz frequency rate. 

For the video input and video output we used respectively HDMI input IP and HDMI output IP that already existed. The HDMI input component (ADV7611) and the HDMI output component (ADV7511) are configured by software at start up.

A UART interface is used to communicate and configure different part of the system (HDMI, VDMA, VTC).

The Xilinx® LogiCORE™ IP AXI VDMA core provides the high-bandwidth direct memory access between the DDR4 memory and the HDMI peripherals.

This is a simplified view of the hardware design using Vivado 2017.2

Software design

Our demo is a bare-metal application executed on the ARM Cortex A53 processor. The project was developed with SDSoC2017.2 from Xilinx.

In our software the edge detection code is accelerated in hardware to improve performances.

The edge detection algorithm is producing a black and white video stream. Edges in each frame are marked as white and the remaining part of the figure is set as black.

The edges are detected by a Sobel filter. Each pixel is filtered by a 3x3 2D FIR filter. A nonlinear decision on the output of the filter provides information as to if the pixel is part of an edge or not. All computation is performed in fixed point. The Sobel filter is applied on the left half of each video frame for display purposes.

When the filter is accelerated, the main purpose of the software code is to control the advancement of VDMA frame pointers. Indeed, a triple buffer is used in order to display the newly computed frame a soon as the Sobel filtering is finished while, at the same time, processing the following input frame.

The output display is vertically split in half. The right side displays the video before being processed while the left side displays the video processed with a Sobel filter.

The software has been developed to highlight the benefit of hardware acceleration. In that respect, the output video display switches between the data processing done in software then done in hardware. The changes occur about every 15 seconds and highlights the greater performances achieved once the software is accelerated. In our case, the FPS is closed to 40 times faster:

·         0.73 fps (software)

·         31 fps (hardware accelerated)


This video demonstrates the use of the Lynsyn board to monitor the power usage when running the EMC2 HDMI in to HDMI out application with hardware accelerated Sobel filter.

  • 1 × EMC2-ZU3EG PC/104 OneBank Board w. Zynq ZU3EG MPSoC FPGA developed by Sundance Multiprocessor Technology Ltd.
  • 1 × VITA 57.1 FMC-IMAGEON HDMI input/output FMC card that provides high definition video interface for Xilinx FPGAs
  • 1 × TE0820-02-03EG-1E MPSoC Module with Xilinx Zynq UltraScale+ ZU3EG-1E, 4 x 5 cm, 1 GByte DDR4 developped by Trenz Electronics
  • 1 × STC-HD93DV HD DVI Output CCD, 720p, Color, Cased by SenTech

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kumar090192 wrote 07/10/2022 at 08:48 point

Hi, Can anyone share the application project (Vitis Project). I made but I am facing one error #include "sds_lib.h" is not there because of the build is failing. 

  Are you sure? yes | no

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