Algol RISC-V CPU for CAT iCE40 FPGA Board

I had some problems getting the Algol CPU tests compiled and run:

1. The compiler I built didn't recognize the "-m32" flag specified in the makefile.
2. The "riscv_test.h" header file was missing.
3. The tests would stall because a memory leak consumed all the RAM after 25% of the tests were run.

I solved these problems by:

1. Installing an earlier version of the compiler.
2. Grabbing some files from a development branch and adding them into the master branch of my Algol repo.
3. Increasing the RAM size of my VM. (This doesn't fix the root cause, but avoids memory exhaustion before the end of the tests.)

With these changes, I decided to record a complete set of the steps to get to this point in case I need to do it again.

First, create the VM and start it up:

mkdir xenial64
cd xenial64
vagrant init ubuntu/xenial64

Edit the Vagrantfile to increase the RAM size:
      config.vm.provider "virtualbox" do |vb|
        # Customize the amount of memory on the VM:
        vb.memory = "4096"
      end

vagrant up
vagrant ssh

On the VM, install an earlier version of the RISC-V compiler that was originally used to test this CPU:

sudo apt-get update

sudo apt-get install autoconf automake autotools-dev curl libmpc-dev libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo gperf

sudo mkdir /opt/riscv
sudo chown $USER /opt/riscv

git clone https://github.com/riscv/riscv-gnu-toolchain
cd riscv-gnu-toolchain
git checkout f2a2c87

mkdir build; cd build
../configure --prefix=/opt/riscv
make -j$(nproc)
make distclean

Edit ~/.profile to add:
    export RISCV="/opt/riscv"
    PATH="$RISCV/bin:$PATH"

source ~/.profile

I modified my Algol repo to add the "env" directory I found in the "develop" branch into the "master" branch:

git clone https://github.com/xesscorp/algol
git branch develop origin/develop
git checkout develop -- Simulation/tests/riscv_test/env
git commit -m "Added env directory needed for compiling tests."
git push origin master

Install the Algol CPU repo on the VM:

git clone https://github.com/xesscorp/algol
cd ~/algol

Install Python and MyHDL in order to simulate the CPU:

sudo apt-get install python-minimal python-pip
sudo pip install myhdl

Finally, compile and run the Algol CPU tests:

./main compile_tests
./main core -a

That's it!

There are 115 tests in the suite: 96 passed and 19 failed. The failures were the timer instruction, the fence_i instruction, and all the atomic memory operation (amo*) instructions.

At this point, I have a (mostly) working simulation of the Algol CPU in MyHDL for me to start experimenting on.

On my Win7 machine, I created a linux VM to host the RISC-V toolchain:

$ mkdir xenial64
$ cd xenial64
$ vagrant init ubuntu/xenial64
$ vagrant up
$ vagrant ssh

Then I built the toolchain on the VM:

$ sudo apt-get update
$ git clone https://github.com/riscv/riscv-tools.git
$ cd riscv-tools
$ git submodule update --init --recursive
$ sudo apt-get install autoconf automake autotools-dev curl device-tree-compiler libmpc-dev libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo gperf libtool patchutils bc zlib1g-dev pkg-config
$ export RISCV=/home/ubuntu/riscv
$ export PATH=$PATH:/home/ubuntu/riscv/bin
$ ./build.sh

Unfortunately, the build.sh failed. I tried some other linux distros (ubuntu/trusty64, debian/jessie64) without success: the toolchain failed to build for a variety of reasons. Finally, I edited the build.sh file to remove the build of the riscv-openocd tool. (I figured I wouldn't need the on-chip debugger right now.) After that, the build was successful. 

The first step in this project was to clone Angel Terrone's Github repo for the Algol RISC-V CPU. Then I created a dependency graph for the MyHDL files that describe the processor:

In parallel with understanding the processor architecture, I have to get the software toolchain installed and running on a linux VM.