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Ternary VHDL package v1.0 is ready

A project log for Homebrew ternary computer

TRIADOR: The only ternary computer made for real in the past 50 years.

SHAOSSHAOS 07/06/2018 at 09:300 Comments

So now we have everything to build a ternary computer in binary CPLD (or FPGA)::

https://cdn.hackaday.io/files/285791222723936/ternary.vhd

Last pieces were just added:

- procedure dmux:

        PROCEDURE dmux(signal T_S: IN FakeTrit;
                       signal T_C: IN FakeTrit;
                       signal T_N: OUT FakeTrit;
                       signal T_O: OUT FakeTrit;
                       signal T_P: OUT FakeTrit) IS
        begin
                case T_S is
                when N =>
                        T_N <= T_C;
                        T_O <= O;
                        T_P <= O;
                when O =>
                        T_N <= O;
                        T_O <= T_C;
                        T_P <= O;
                when P =>
                        T_N <= O;
                        T_O <= O;
                        T_P <= T_C;
                when others =>
                        T_N <= X;
                        T_O <= X;
                        T_P <= X;
                end case;
        end;

- component ternary_mem:

-- Entity ternary_mem

USE ternary.ALL;

ENTITY ternary_mem IS
        PORT (
              T_S : IN FakeTrit;
              T_N : IN FakeTrit;
              T_P : IN FakeTrit;
              T_Q : OUT FakeTrit
        );
END ternary_mem;

ARCHITECTURE Behavioral OF ternary_mem IS
BEGIN
    PROCESS (T_S)
    BEGIN
        IF (T_S(0) = '1') THEN
            T_Q <= T_P;
        ELSIF (T_S(1) = '1') THEN
            T_Q <= T_N;
        END IF;
    END PROCESS;
END Behavioral;
  - component ternary_clock:
-- Entity ternary_clock

USE ternary.ALL;

ENTITY ternary_clock IS
        PORT (
              B_C : IN BIT;
              T_C : OUT FakeTrit
        );
END ternary_clock;

ARCHITECTURE Behavioral OF ternary_clock IS
signal flag : bit;
BEGIN
    PROCESS (B_C)
    BEGIN
        IF (B_C'event AND B_C = '1') THEN
            IF (flag = '0') THEN
                flag <= '1';
            ELSE
                flag <= '0';
            END IF;
        END IF;
        IF (B_C = '1' AND flag = '0') THEN
            T_C(0) <= '1';
        ELSE
            T_C(0) <= '0';
        END IF;
        IF (B_C = '1' AND flag = '1') THEN
            T_C(1) <= '1';
        ELSE
            T_C(1) <= '0';
        END IF;
    END PROCESS;
END Behavioral;

Last one turns binary clock into ternary sequence NOPONOPONOPO...

Also I renamed some variable names and added additional components for mux and dmux ( just in case if somebody doesn't like them as functions ; )

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