2019-02-22

JEDEC files for the two PAL chips arrived, thanks to Andy!

2019-02-23

JED files decompiled. A bit worried the pinout might differ from the manual I have (for a later version hardware). Partly a red herring, the decompiler produces expressions for i/o pins that are used as inputs, but the output is disabled so there is never a conflict. I did find some difference in the rest of the circuit but I don't have to worry about that for the purpose of recreating the logic chips.

2019-02-24

I now have a better understanding of what is going on in the PAL chips. I already have ideas to tweak it to use a 512K RAM chip (instead of two 8K or 32K chips). It has two 8K chips right now, which is fine for testing but one might like to do something more serious.

2019-03-14

Translated the logic files, compiled them with WinCUPL and programmed two 16V8 chips which I put in the board with the ROM that came with it. Nothing came through the serial port, which may be normal since I don't know what the ROM was meant to do. The 8 MHz CPU clock is being halved for the SCC clock, so that is one thing that is definitely right. The CPU is being held in a wait state, because it is doing a read cycle with none of the programmable chip selects active, which becomes an STEbus cycle. As there is nothing there, it waits forever. This may be normal too, since I don't know if it expected a slave board there.

For now I will just have to assume the logic is correct and use test code to prove or disprove it.