I've got a bit further analysing the equations than the files uploaded on the 13th March, but for some reason I am unable to upload files as of now.

The 68008 board PAL chips provide good hints about the logic. 

The 68000 logic seems to be complicated by the fact the data bus interface is neither 8-bit (like the 68008) nor can it be made so by dynamic bus sizing (like the 68020).

Instead, the logic appears to generate two 8-bit STEbus cycles for every 16-bit CPU cycle.

One of the bytes is temporarily held in a latch (a 74ACT646) while the other passes through a buffer (a 74ACT245). These present two bus loads that are in total probably less than one LS TTL load.