There are two oscillators on the SBC, Y1 and Y2. Unfortunately, the information on what these are is missing!
Y1 is "XOSC" and is 24 MHz, from which the 3 MHz quadrature ECLK and QCLK signals for 63C09 U3 are derived inside of CPLD U7.
Y2 is "WOSC" and is 14.745 MHz, which CPLD U7 divides by 8 and 4 to produce the signals that are applied to SCC U5 ACLK and BCLK, respectively.
Below is a snippet from the HD6309_glue_top.vhd file documentation, which seems to be the only place I bothered to document this information :-/
entity HD6309_glue_top is port ( XOSC : in std_logic; -- Oscillator input for CPU (nominally 24 MHz) WOSC : in std_logic; -- Oscillator input for ACLK/BCLK (nominally 14.745 MHz) QCLK : out std_logic; -- Q phase clock output (nom 3 MHz, XOSC divided by 8) ECLK : out std_logic; -- E phase clock output (nom 3 MHz, XOSC divided by 8) BCLK : out std_logic; -- SCC ch B baudrate (WOSC/4 for SCC BRG) ACLK : out std_logic; -- SCC ch A baudrate (WOSC/8 for 115.2kbps in SCC 16x mode)
Possible source for Y1 (DigiKey): https://www.digikey.com/products/en?keywords=SER1213-ND
Possible source for Y2 (DigiKey): https://www.digikey.com/products/en?keywords=SER1234-ND