I recieved my hd6309 SBC bridge PCB right around Easter time. This is just a small PCB that interfaces to the expansion connector on the SBC. It brings the address, data, control lines through 5V to 3.3V level shifters (74LCX541 and 74LCX245 do the work here). A 40-pos ribbon cable interfaces these shifted signals to my Terrasic DE1 FPGA dev board. The DE1 is a fabulous board with an Altera Cyclone II FPGA and a very rich set of peripherals included (SDRAM, FLASH, SRAM, CODEC, LEDs, Switches, RS232, VGA...the list goes on).
After a simple I/O port implemented in the FPGA as a test (read the DE1 switches, write to the DE1 LEDs) I tore into a very nicely done GPL VHDL model of a Yamaha YM2149 sound chip (courtesy of MikeJ at FPGAArcade.com). The YM2149 is essentially an AY-3-8910 at heart. I altered the bus interface section to provide a demultiplexed bus (A0-A3 inputs, RD strobe, WR strobe) and removed the YM2149's two 8-bit I/O ports. I implemented a very simple address decoder of the hd6309 CPU address lines, and routed the audio out via the DE1 onboard CODEC. Voila! The hd6309 SBC now can make cool beepy-boopy sounds via a synthesized YM2149 soundchip.
This was a nice diversion that definitely proves out the idea that an FPGA can easily be interfaced to the vintage hd6309 CPU. As I wrote earlier, the intent is to eventually implement an FPGA-based VGA video controller, sound chip, PS/2 keyboard interface, and a paged MMU for RAM expansion. Sure, the FPGA could hold the CPU, also, but that's not what I'm after, here, so I'll stick to actual hardware for the CPU!