Word size: 6 trits = 1 trite
Max addressable memory: 3^12 = 531 kt (kilotrits) = 0.76MB
The design will be fully ternary in the CPU core with binary SRAM for memory (using a binary coded trinary scheme). The goal is to operate the machine at around 1 million instructions per second.
Memory address will be 2-trites wide or else I'd be limited to only 729 trites of memory which is too little for my goals. This means a hybrid 6/12-trit architecture. Given the added complexity of double width registers it may make sense to build the whole machine at 12-trits wide. The main concern is the full adder which is very heavy on electronics.
Register Set:
A | Accumulator (trite) | |
B | Operand Register (trite) | |
SP | Stack Pointer (2-trites) | |
IX | Index Register (2-trites) | |
PC | Program Counter (2-trites) |
All ALU operations store the result in A. All single parameter ALU operations use A as the source. All dual parameter operations use A and B as the source operands.
Hi. I want to implement LISP in my #Coolsystem project. Need your help.