John SullyI've been a little bit worried about the ease of construction of my 20 instruction ISA, so I've put here a simplified version. This should still be sufficient to get a useable machine albeit with significant performance penalties. At only 11 instructions this design would require much simpler hardware.
| Mnmonic | Name | Operation |
| Arithmetic And Logic | ||
| NAC | Negate Accumulator | -A -> A |
| AAC | And Accumulator | A & B -> A |
| OAC | Or Accumulator | A | B -> A |
| XAC | XOR Accumulator | A XOR B -> A |
| ADD | Add Accumulator | A + B -> A |
| SUB | Subtract Accumulator | A + (-B) -> A |
| Branch and Test | ||
| JAF | Jump Flags (Indirect) | if (op1 & flag) then (PC + 2 + op2) -> PC |
| Load and Store | ||
| SWP | Swap | A <-> B |
| LIM | Load Immediate | op1 -> A |
| IO | ||
| OUT | Output to terminal | A -> Term Device |
| IN | Input from terminal | Term Device -> A |
This design does not need a stack pointer or an index register. All jumps are relative. Unconditional jumps can be simulated by testing the True flag which is always true. This will likely be the ISA of my first machine but it will make implementing higher level languages tedious and the performance will be poor.
I'm also toying with the idea of some sort of trap infrastructure so I can emulate the missing instructions in software.
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