Build a Logic probe out of a cellphone display
While this project is finished and usable, there is plenty of space in the FPGA for enhancements. There is no processor in this design, I created a statemachine inside the FPGA that handles the GUI input and display. I want to add support for up to 4 channels that can be connected via test leads. The design currently uses a 128Kbit SRAM insided the FPGA, but the circuit also has a 4Mbit SRAM which will be plenty fast enough to support 4 channels. Also, the triggering is very simple right now, I often need the ability to trigger on pulse width times (eg, if a pulse is longer or outside some programmed range). Also, the zoom capability isnt working, need to fix that. I also want to recognize and display SPI or UART characters.