• Problems with testing the SRAM with an AVR

    Ethan Durrant • 01/07/2015 at 04:05 • 0 comments

    So, I decided to test my DIY Latch circuit along with the memory by using an ATmega8515 AVR microcontroller to try writing to , and reading from the SRAM chip. In theory, this wouldn't be difficult because the ATmega8515 conveniently has support for using external memory in much the same way as the 8085 microprocessor (also needs the latch), but in testing, not so great. I wrote some code for the AVR that writes the values 0-255 into address locations 0-255 in the SRAM chip then tries to read them back and compares, to see if the write was successful. But instead of doing the full program, the AVR hangs when it reaches the point where it must read from the SRAM chip, and gets stuck. This must be a problem with reading in hardware, I just can't seem to find what is the problem, but I think that it could have to do with my DIY Latch circuit not being entirely up to spec. Well, if anybody who is actually bothering to read this Log has any ideas or advice to help with this problem, feel free to comment.

    Here are some pictures with everything rigged up (it's a glorious mess of wires!):

    a close up of the wiring for the 8K x 8 bit SRAM chip ( MT5C6408 )

    other pics:

    Hopefully I get this working soon. If not, I may just give up on my DIY Latch Circuit and actually spend some money to get bunch of 74x573 type Octal latches. which are known to work in this type of setup.

  • Dealing with my lack of a latch IC by building one with 7400 series logic.

    Ethan Durrant • 01/04/2015 at 23:57 • 0 comments

    The 8085 microprocessor uses a multiplexed data/address bus to interface with memory. The lower 8 bits of the memory address bus share the same output pins as the 8 bit I/O or data bus, these are meant to be multiplexed using an external Latch IC such as a 74F373 or 74HC573 Octal D-type transparent latch which is enabled by the ALE pin on the microprocessor. Using this method, it writes the upper and lower half of the memory address while the Latch is enabled, then it disables the Latch (but it continues to hold it's I/O states for the address while disabled) and uses the pins for data transfer between the microprocessor and memory until it needs to access a new address. The problem in my situation is that I lack any suitable Latch IC to make this multiplexed bus work, but I have a plan to solve that problem, which is probably the hard way ( but not the hardest ). That plan is to just create the identical latch circuit using 7400 series logic ICs. Sounds simple right? Well it is, somewhat...

    So I start by scrutinizing the datasheets of two Latch ICs that I know work for this situation and trying to figure out how exactly they work. One of those is the 74HC573, which is described as "Octal D-type transparent latch". So I searched for "D-type transparent Latch" and found the description and a logic diagram for it in the Wikipedia article on Flip-Flops.

    Here is the image of the logic circuit from Wikipedia that I chose to use, due to the fact that it uses 4 NAND Gates, so I can make it using a single 7400 Quad NAND Gate IC.


    I then took the drew a diagram of a 7400 Quad 2-Input NAND Gate IC on paper and traced out the connections I should make on it in order to create a D-type transparent latch.

    I then proceeded to create the circuit and test it on a breadboard. The Green LED is the Q output, and the red LED is the inverted-Q output, the white wire is the D input, and the green wire is the E or enable input. The Q ouput green LED is ON because the D input is HIGH and the Latch is enabled with the E input HIGH, the inverted-Q output on the red LED is of course OFF because it's the opposite of Q.


    Now that I know that the circuit works, it's time to add the "Octal" part of it by making a total of 8 of these D-Latches as is shown in the 74HC573's datasheet:

    Finally, after stripping many wires, I have the breadboard packed to the brim with 8 74LS00 ICs and completed D-Latch circuits!

    A close-up of the circuits:

    Going through the line, testing each circuit with my 2 LED setup and jumper wires:

    Now all that's left is programming and wiring up some memory to test if this all works! I'm thinking of putting just a SRAM IC on the breadboard and using a microcontroller to load a program into the memory at boot time. Probably going to be a similar setup to what Quinn Dunki did for her Veronica computer using an AVR and SRAM, link here.

  • 8085 Free Run Test successful!

    Ethan Durrant • 01/04/2015 at 06:43 • 0 comments

    I set up a basic free run circuit (makes the CPU read the NOP/"no operation"/0x00 instruction from the resistors tied to ground and then cycles through all it's memory address space in a loop) and can see the output of the top two address bits on the LEDs which are flickering rapidly. I copied the circuit from the MAG-85 project on http://saundby.com/electronics/8085/freerun.shtml


    Here are some close-up photos of the circuit on the breadboard: