Updates: Status, Maker Faires, and the Future

A project log for MENTAL-1, a Brainfuck CPU

A minimalist computer for a minimalist language

Trey KeownTrey Keown 01/23/2018 at 08:340 Comments

The past few months have been slow for MENTAL-1, but a few important milestones happened. Most importantly, I'm officially calling it finished. The MENTAL line of processors is most definitely not, but MENTAL-1 is. It's able to achieve stable operation at 3MHz, has working peripherals that were designed for it (the PS/2 keyboard input and the 40x2 character display output), and most importantly has a slick laser-cut case. I've included the most recent video I have of it in operation - it's one I created for showing the computer to a few different Reddit communities.

One of the best things to come from this project was being able to use it as a tool to teach others about building their own CPUs. At the Seattle Mini Maker Faire, I had a blast introducing the ideas behind how computer chips are made, how digital logic works, and how creating a large hand-wired project like this can be tedious but incredibly rewarding.

Demonstrating digital logic. I had a breadboard hooked up with a NAND gate, NOR gate, and NOT gate. Visitors could toggle switches to see how that makes the outputs change.

The CPU was running the simple "cat" program I had written, and visitors were able to stop by and type out any message they wanted. The new case on it helped keep my mind at ease when the younger crowd stopped by and wanted to get hands-on.

My CPU had a bug during a few demonstrations.

I was able to attend the Wenatchee Mini Maker Faire as well, which was much more relaxed but still a great time. It was a bit after the one in Seattle, so I had time to polish my presentation a bit.

Rocks, the elements extracted from them, and silicon wafers (which are made of those elements) are on the right side of the table.

It's been a blast sharing this with local communities.

So, what's the plan now? MENTAL-1 is finished. I've started work on MENTAL-2, which is fairly messy but much more compact. I'm currently working on an FPGA implementation as well.

I'll post proper schematics, the source code for my "cat" program, and my notes here in the coming months.