This is an architecture inspired by the PowerPC 970 with some of its complexities removed (dynamic execution more like a 7400). I left some of the branch execution to the programmer to avoid complex branch prediction, and so that the pipeline would only have to worry about data hazards. A branch's instruction is quickly decoded and used to fetch the next instruction, thus eliminating pipeline bubbles and the need for ridiculous dynamic execution to avoid such bubbles. However, this leaves a problem for the programmer because if the programmer had an instruction to compare two numbers and store the result in the flag register with a branch immediately afterwards, the branch would be looking at old data. As such, a programmer must write the comparison instruction several instructions before the branch, either with noops or arithmetic in-between. I may eventually attempt to build this in Logisim.