• Overall Specifications

01/04/2016 at 04:38 0 comments

This is somewhat a living document. It may change if a certain requirement is discovered to be difficult to implement and fails a cost benefit analysis. The next step is to use it to generate a block diagram of the proposed system.

Basic Purpose

Preform additive synthesis with square waves.

Sum square waves of arbitrary magnitude and output the result as audio, a control voltage, and a visualization of the resulting waveform. The square waves frequencies are multiples of a fundamental frequency. If the fundamental frequency is 100 Hz, the other available frequencies will be [200, 300, …, 800] Hz.

The output fundamental frequency range will be decided during the design phase. As a minimum it should cover [0.1, 100] Hz for use as a LFO. Ideally it should go up to 10 kHz, in order to cover the useful audio range.

Requirements

• Provide ability to be controlled by an external envelope generator. (Research if this is commonly done, or if a signal and its envelope are multiplied externally.)
• Provide ability to reset all harmonics to 0ᵒ phase via both push button and external control voltage.
• Provide ability to pause output waveform (probably by disconnecting the clock from the divider network) via both push button and external control voltage.
• Hopefully it can be powered by two 9 V batteries, stepped down to 5 V. If not, include a barrel jack and wall wart, with appropriate voltage conditioning circuitry.
• Provide ability for user to know if batteries are almost dead.
• Provide LED whose brightness changes with the output voltage amplitude. Useful for LFO applications.

Summary of Method

Generate an initial high frequency square wave and frequency divide it down to the desired harmonics. Sum the harmonics. Provide the ability to control the summing coefficients and invert individual harmonics to get a negative summing coefficient.

Currently I don’t know how to change the phase of each harmonic while still being able to optionally keep them in phase and at the correct multiples of each other (at least using analogue techniques).

Inputs Accepted

• External clock signal
• A Reset control voltage
• A Pause control voltage

Outputs Available

• The summed square waves: Audio (speaker), trs jack, bnc jack, tiny oscilloscope screen.
• A saturation warning light, which flashes if the summing circuit hits the voltage rail.
• A low power LED, which turns on when the batteries are almost dead.

User interface

• Each available harmonic needs a sliding pot to control the harmonic and a switch to control its polarity (adds 180ᵒ phase).
• Provide a switch to change between internal clock and externally provided clock.
• A Reset button, which resets all harmonics to 0ᵒ phase.
• A Pause button, which pauses the output waveform at its current value. When button is released the waveform resumes from where it was paused.
• Project Management

01/03/2016 at 07:05 0 comments

Edit: The Engineering Art Show is no longer happening, so this project has been pushed back in priority.

If I'm going to finish this project in a month, I will need some way to plan out the entire thing. Enter Gantt charts. I've never made one before, but a quick google search told me that GanttProject is an open source program I can use to make them.

I've tried to make this one as general as possible so I can use it on other projects.

I'm not experienced enough to know how long some of the design steps will take so I'm using it more like a flow chart that tells me what to focus on. As an example, I would sometimes become distracted by sourcing parts. With this plan, I know I can leave it alone entirely.

Also, after making this it seems like there's no way I'll be done in a month. I think I will still push for that goal, but set a new hard deadline of two months. The UofA Engineering Art Show is at the beginning of March, and this would make a great entry.

• System Block Diagram

06/12/2015 at 11:36 0 comments

Here's the overall block diagram. It was developed from the overall specifications. Explanations of each block are below:

External Input Frequency: This lets the user input their own initial frequency.

Inputs: A TRS jack (phono jack)mounted on the face plate.

Outputs: A square wave. Acceptable frequency range will be determined during prototype characterization.

Initial Frequency Generator: Generates the initial high frequency that is divided down into all the desired harmonics. It will be a 555 timer or relaxation oscillator or whatever else produces a desirable square wave.

Inputs: Face plate user controls (pots, switches) which control frequency.

Outputs: A square wave. Acceptable frequency range will be determined during prototype characterization.

Clock Interrupt: By disconnecting the clock from the harmonic generator, the devices output will pause as all the flip flops and counters hold their state.

Inputs: A SPST off-mom switch mounted on the face plate and the initial frequency signal.

Outputs: The initial frequency signal or 0 V.

Phase Reset: This signal will reset the counters and flipflops to their initial state, effectively resetting the device's output to zero degrees phase.

Inputs: A DPST off-mom push button switch mounted on the face plate.

Outputs: A +Vcc and a gnd signal when off. They switch when the button is pressed.

Harmonic Generation: This takes the initial frequency and pulls out all the desired harmonics. It's a series of chained frequency dividers realized with T flip flops and counters. The total division ratio is 1680:1. In other words, if a 1680 Hz frequency is input, the output fundamental frequency will be 1 Hz.

 Input f Output fundamental f 1680 Hz 1 Hz 168 Hz 0.1 Hz 168 kHz 100 Hz 16.8 GHz 10 kHz

From the above table it's clear that, while an output of 10 kHz is not possible without delving into RF theory, something like 300 Hz should be possible.

Inverting: Each output harmonic will have the ability to be inverted, giving me the ability to produce negative Fourier coefficients. In reality there are 8 inverters, each with their own switch, which aren't shown for simplicity.

Inputs: The square wave harmonics and eight toggle switches mounted on the face plate.

Outputs: The square wave harmonics that are possibly inverted.

Summing: All the components will be fed into an inverting summing op-amp stage, which will let me control the amplitude of the harmonics individually and as a group. The design will be such that each waveform is at maximum amplitude 1 Vpp to help avoid clipping.

Inputs: Eight 1 Vpp square waves. Eight slide pots mounted on the face plate to control individual amplitude. One slide pot mounted on the face plate to control overall amplitude.

Outputs: The summed square waves, max voltage = 5 V.

Output Jack: This let's the user extract the created signal for additional manipulation/use.

Inputs: The summed square waves, max voltage = 5 V.

Outputs: Trs and BNC jacks mounted on the face plate.

Waveform Display: This is an XMEGA Xprotolab, a tiny oscilloscope that will be mounted to the case. It will enable a more instinctive control of the harmonics present in the output.

Inputs: The summed square waves, max voltage = 5 V. Also the XMEGA and all its controls mounted on the face plate.

Outputs: An image of the output waveform.

Speaker Driver: This will be an LM386 op amp connected as recommended in its datasheet. It will have user controllable gain, which means there will be two ways to change the overall gain of the audio signal.

Inputs: The summed square waves, max voltage = 5 V. Also a rotary pot mounted on the face plate to control volume.

Outputs: A buffered version of the input able to drive an 8 Ω speaker.

Speaker: Mounted to the enclosure to let you hear what you're creating.

Inputs: The buffered output waveform.

Outputs: An audio signal of crystal clarity.

9 V Battery: Each battery will be used to form one of the power rails.

Inputs: N/A

Outputs: 2x 9V in series, center grounded.

Power Supply: This will be a basic ±5 V linear voltage converter design.

Inputs: Power from 9 V batteries.

Outputs: Constant ±5 V rails.

Power Status LED + Driver: This LED lights when the batteries drop below 5 V. It will be either an op amp comparator, ASIC, or something clever with BJTs. (Priority given to solution with lowest power draw.)

Inputs: 9 V batteries (or the voltage regulators if that works better).

Outputs: Panel mounted LED that lights when power is low.

I may also include a LED whose brightness changes with the output voltage amplitude. It would be buffered with a bjt voltage follower.

• PCB Design

06/07/2015 at 08:13 0 comments

Note: this log was created in 2015 and may not be valid anymore. Starting January 2016 I'm going through the design process systematically and may add or change details.

The general approach will be to put the initial frequency generator, divider network, and summing op-amp on three different boards and then stack them. I want to be able to swap out the initial frequency generator if I find a design that can produce a higher frequency, and the summer is easy enough to assemble on perf board. The divider network, however, has a lot of connections and would be a mess if I used perfboard. I can also use this chance to learn how to use Eagle.

• Frequency Division Scheme

05/26/2015 at 09:59 0 comments

Note: this log was created in 2015 and may not be valid anymore. Starting January 2016 I'm going through the design process systematically and may add or change details.

I'm calling this part of the project the division network. It's the part that takes the initial high frequency square wave and pulls out all the harmonics (which are then sent to the summing op-amp).

First, I found circuits which I could blackbox and just think of as (with regards to frequency) "divide by n".

In general, you can make a "divide by n" circuit by using the input pulse as a clock, and then pulsing the output every n pulses. The IC I found which does this is the CD4017B, a CMOS Counter/Divider (TI Datasheet). I picked the SOIC 16 package.

Here's the "divide by 2" circuit:

Now that I have blackbox dividing circuits, here's the block diagram for the divider network:

To find this configuration I tried every possible way of dividing 840 by its factors to get the desired harmonics, 840 being the LCM. I chose the way that used the least number of divisions, letting me chain multiple outputs together.

Something that kind of sucked was that originally the 8 Hz signal was coming out of the divide by 7 block. I had to double the input frequency oy to 1680 Hz and add an extra divide by 2 block. This will end up halving the maximum output frequency of the project.

The dashed boxes indicate which divide by 2 blocks share an IC.

Also note that, although the outputs are labeled numerically, the input frequency will be variable. I labeled the circuit nodes that way to make sure my math was right.

This is a bit nitpicky, but I noticed something after I had designed the pcb for this project. If I want to decrease the presence of high frequency signals on the board, I should rearrange the divide by n blocks to divide by the larger numbers first. In the case of U1 - U3, instead of having 560 Hz, 112 Hz, 16Hz, I could instead get 240 Hz, 48 Hz, 16 Hz. However, I don't think it will be that big of a deal and doesn't justify changing all my documentation and design. If I had proof it would be a problem I would put in the effort, but at this point it's just a small maybe.

That concludes the theory of the divider network. Check the PCB Design project log for the implementation.

• Initial Frequency Generation

05/26/2015 at 09:56 0 comments

Note: this log was created in 2015 and may not be valid anymore. Starting January 2016 I'm going through the design process systematically and may add or change details.

The chosen design involves generating an initial square wave and then frequency dividing it. This section talks about how to generate that initial waveform.

The easiest way I can think of to generate a square wave is with a 555 timer. Other methods would include an opamp relaxation oscillator or a comparator/integrator circuit.

Because of all the dividing necessary, the initial frequency is quite high. if I want a 1 kHz output signal, the initial frequency would have to be 1.26 MHz. That's getting pretty high, and I'm not sure if that's within the 555's frequency range.

The circuit used is shown below (image from wikipedia). Note that C is really C1.

According to "Practical Electronics for Inventors", the equation for the frequency of a 555 timer in astable mode is:

The goal here is to use this equation to find something I can change to sweep over an entire decade of frequency, say from 100 Hz to 1000 Hz, and also something I can change to switch which frequency decade I'm sweeping over. The easiest implementation was to change C1 by an order of magnitude to jump decades and then vary R1 or R2 with a pot. After using excel for a bit, it was found that it was better to vary R2 in terms of component values needed versus what is available on digikey. Another thing to keep in mind is that frequency controls usually have course and fine adjustment knobs. This translates into R2 being composed of two pots, one ten times larger than the other. This produces some weird maximum resistance values for R2, like 1100 Ω or 550 Ω. Also, there needs to be some small constant resistance added, to ensure R2 does not reach 0 Ω.

I wanted the frequency ranges to overlap a bit so I could be sure of covering every frequency. For a given decade, it seemed like [0.8, 12] would be a good range to cover.

The frequency division network divides the input frequency by 1680 to produce the fundamental harmonic. This means that whatever the initial frequency is, it is divided by 1680 to arrive at the output frequency for the device.

With all of that in mind, I played around in excel until I found component values that met my needs:

C1a = 900 nF, C1b = 90 nF, C1c = 9 nF, C1d = 900 pF

R1 = 68 Ω

R2 = 500 Ω pot + 50 Ω pot + 5.6 Ω

The figure below shows the overlap of the frequency range. Each line is a different capacitor value, with R2 being swept over its resistance range.

Note that the above figure shows the frequency after the divider network, not the frequency output by the 555 timer. The maximum value of the initial frequency in this design is 20.2 MHz. I'm pretty sure that's way too large, but let's give it a go anyways.

I assembled the circuit on a breadboard:

It didn't oscillate. I found that R1 was too low. Modifying the design a bit, I multiplied both R1 and R2 by 5 and divided C1 by 5. Lucky, the necissary components seem to be avaliable on digikey. New values are:

C1a = 180 nF, C1b = 18 nF, C1c = 1.8 nF, C1d = 180 pF

R1 = 340 Ω

R2 = 2500 Ω pot + 250 Ω pot + 27 Ω

I tried these values and found that they weren't behaving nicely. So. instead of fooling around with it anymore, I'm going to move to a relaxation oscillator circuit, shown below. I've built this circuit a few times and am confident I can get it to work.

To explain it briefly, R2 and R3 control the value to which C1 has to charge before the output polarity is switched, and R1 controls how fast C1 can reach that value.

It needs a dual rail power supply, so I will be splitting 5 V using the ever useful TLE2426.

Wikipedia gives its output frequency formula as:

Their derivation set all the resistors equal when they don't have to be. All the resistors can be different, as long as you keep in mind how changing the voltage division ratio affects the circuit.

After some excel, I found the following values gave the desired [0.8, 12] frequency range for a given decade:

C1 = 12nF

R1 = 25 kΩ pot + 2.5 kΩ pot + 2.2 kΩ

R2 = R3 = 100 kΩ

With a range of R1 of [2.2, 29.7] kΩ , the frequency range is [1.28, 17.2] kHz. After dividing by 1680 for the division network, it comes to {0.76, 10.26] Hz. To get decades other than the 1 Hz, I will increase/decrease C1 by an order of magnitude.

I'm partial to the TL072 op-amp, since I've seen it everywhere in synth schematics.

I tried 4 different capacitor values and found the R1 value which made the circuit oscillate at 1.34 kHz and 20.16 kHz. (The values for a frequency of 0.8 kHz and 1.2 kHz after the divider network.)

• Matlab code to show end result

03/03/2015 at 08:56 0 comments

Below is code you can run in matlab to see what this project will output when it's done. Change the values of a - f to generate different waveforms. (In general, keep the values between 0 and 1.)

t = 0:0.001:4*pi;
y1 = sign(sin(t));
y2 = sign(sin(2*t));
y3 = sign(sin(3*t));
y4 = sign(sin(4*t));
y5 = sign(sin(5*t));
y6 = sign(sin(6*t));
y7 = sign(sin(7*t));
y8 = sign(sin(8*t));

a = 1;
b = 0.2;
c = 0;
d = 0;
e = 0.5;
f = 0;
g = 0;
h = 0;

sum = a*y1 + b*y2 + c*y3 + d*y4 + e*y5 + f*y6 + g*y7 + h*y8;

plot(t,sum)
axis([0,15,-3,3])