Tagged registers: type

A project log for PDP - Processor Design Principles

Distilling my experience and wisdom about the architecture, organisation and design choices of my CPUs

yann-guidon-ygdesYann Guidon / YGDES 10/19/2021 at 02:360 Comments

Log 27. Tagged registers talked about "hidden"/"restorable"/"implicit"/caching tags.

There is another type of register tag that is explicit and directly interacts with the ISA, the programs and their state. In this case, the goal is to move the ever-appearing size and SIMD flags of many instructions, to the register set.

This saves at least 3 bits from every instruction so this is a great win in general-purpose processors like #F-CPU. This is less an issue for YASEP and YGREC8 which only deal with single-size values.

However the side effects easily counter-balance this easy win. Trap behaviour must be clearly defined and consistency checks must be sprinkled all over the system.

A simple instruction/opcode like ADD then has many behaviours, depending on hidden values : integer or FP ? scalar or SIMD ? what size ?

The behaviour is not apparent from the opcode alone and we can't know which unit(s) to use at decoding time.

OTOH tagging the registers could be a "cheap and dirty way" to extend an ISA while reusing opcodes with mixed data.