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Reserved opcode values

A project log for PDP - Processor Design Principles

Distilling my experience and wisdom about the architecture, organisation and design choices of my CPUs

Yann Guidon / YGDESYann Guidon / YGDES 02/07/2018 at 17:106 Comments

Instructions are often "sprinkled" in a seemingly random fashion.

I have found a convenient convention/guidance :

It's totally arbitrary and INV is also found as all-0s to catch executing uninitialised RAM.

NOP is also often a special case for some instruction combination. But it's good to give the opcodes special values to ease decoding and extensions. NOP and INV can be pools of unused opcodes for later revisions.

Discussions

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Marcel van Kervinck wrote 03/26/2019 at 17:38 point

I should move these tables to the "data sheets" section on the website as well at some point I guess

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Marcel van Kervinck wrote 03/26/2019 at 09:33 point

Gigatron's vCPU opcodes are jump offsets in the primary page that implements them. For slightly improved readability of hex dumps, I put RET on $FF.

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Yann Guidon / YGDES wrote 03/26/2019 at 13:03 point

do you have an online listing of all the virtual opcodes (and their values) ?
I have seen a description of the physical opcodes at https://www.youtube.com/watch?v=QUfdASs82Lw

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Marcel van Kervinck wrote 03/26/2019 at 17:35 point

Sure, the vCPU ISA definition is part of Docs/GCL-language.txt, and values/addresses/opcodes in interface.json of the GitHub repo: https://github.com/kervinck/gigatron-rom

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Yann Guidon / YGDES wrote 03/26/2019 at 17:40 point

Hah! I was browsing at the same time :-D

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